Application of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel Transistors

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dc.contributor.authorCONTRERAS, Esteban
dc.contributor.authorCERDEIRA, Antonio
dc.contributor.authorALVARADO, Joaquin
dc.contributor.authorPAVANELLO, Marcelo A.
dc.date.accessioned2019-08-19T23:45:09Z
dc.date.available2019-08-19T23:45:09Z
dc.date.issued2010
dc.description.firstpage110
dc.description.issuenumber2
dc.description.lastpage115
dc.description.volume5
dc.identifier.citationCONTRERAS, Esteban; CERDEIRA, Antonio; ALVARADO, Joaquin; PAVANELLO, Marcelo A.. Application of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel Transistors. JICS. Journal of Integrated Circuits and Systems (Ed. Português), v. 5, n. 2, p. 110-115, 2010.
dc.identifier.issn1807-1953
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1079
dc.relation.ispartofJICS. Journal of Integrated Circuits and Systems (Ed. Português)
dc.rightsAcesso Restrito
dc.titleApplication of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel Transistorspt_BR
dc.typeArtigopt_BR
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