Charge-based compact analytical model for triple-gate junctionless nanowire transistors

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dc.contributor.authorAvila-Herrera F.
dc.contributor.authorPaz B.C.
dc.contributor.authorCerdeira A.
dc.contributor.authorEstrada M.
dc.contributor.authorPavanello M.A.
dc.date.accessioned2019-08-19T23:45:12Z
dc.date.available2019-08-19T23:45:12Z
dc.date.issued2016
dc.description.abstract© 2016 Elsevier Ltd.A new compact analytical model for short channel triple gate junctionless transistors is proposed. Based on a previous model for double-gate transistors which neglected the fin height effects, a new 3-D continuous model has been developed, including the dependence of the fin height and the short channel effects. An expression for threshold voltage is presented. The model defines a one-dimensional semiconductor effective capacitance due to the width and the height of the fin, which in turn redefines the potentials and charges, without altering the general modeling procedure. Threshold voltage roll-off, subthreshold slope, DIBL and channel length modulation, as well as, the mobility degradation and the velocity saturation have been introduced into the model. The validation was done by 3-D numerical simulations for different fin heights and channel lengths, as well as, by experimental measurements in nanowire transistors with doping concentrations of 5 × 1018 and 1 × 1019 cm-3. The developed model is suitable for describing the current-voltage characteristics in all operating regions from double-gate to nanowire transistor with only 8 adjusting parameters.
dc.description.firstpage23
dc.description.lastpage31
dc.description.volume122
dc.identifier.citationÁVILA-HERRERA, F.; PAZ, B.C.; CERDEIRA, A.; ESTRADA, M.; PAVANELLO, M.A.. Charge-based compact analytical model for triple-gate junctionless nanowire transistors. Solid-State Electronics, v. 122, p. 23-31, 2016.
dc.identifier.doi10.1016/j.sse.2016.04.013
dc.identifier.issn0038-1101
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1116
dc.relation.ispartofSolid-State Electronics
dc.rightsAcesso Restrito
dc.subject.otherlanguage3-D compact model
dc.subject.otherlanguageFin height capacitance
dc.subject.otherlanguageNanowire JLT
dc.subject.otherlanguageSCE
dc.subject.otherlanguageThreshold voltage
dc.subject.otherlanguageTriple-gate JLT
dc.titleCharge-based compact analytical model for triple-gate junctionless nanowire transistors
dc.typeArtigo
fei.scopus.citations34
fei.scopus.eid2-s2.0-84967332983
fei.scopus.subject3-D numerical simulation
fei.scopus.subjectChannel length modulation
fei.scopus.subjectCompact model
fei.scopus.subjectDouble gate transistor
fei.scopus.subjectFin height
fei.scopus.subjectJunctionless transistors
fei.scopus.subjectThreshold voltage roll-off
fei.scopus.subjectTriple-gate
fei.scopus.updated2024-03-04
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84967332983&origin=inward
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