SOI Stacked Transistors Tolerance to Single-Event Effects

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dc.contributor.authorPerin A.L.
dc.contributor.authorPereira A.S.N.
dc.contributor.authorBuhler R.T.
dc.contributor.authorDa Silveira M.A.G.
dc.contributor.authorGiacomini R.C.
dc.date.accessioned2019-08-19T23:45:27Z
dc.date.available2019-08-19T23:45:27Z
dc.date.issued2019
dc.description.abstract© 2001-2011 IEEE.This paper addresses a quantitative study of the reliability improvement of the stacked transistor structure. The susceptibility of integrated circuits to single-event effects caused by interaction with ionizing particles is analyzed at the semiconductor level, as well as at the device and circuit levels considering the replacement of each transistor by a stacked silicon-on-insulator (SOI) array. Up-To-date technologic nodes were used as inputs for the simulation and reliability models. A stochastic Markov model was proposed and evaluated. The model output pointed the stacked array as a real alternative for high-reliability in future applications, with exceptional results. For a 10^{5} device-count integrated circuit, a success probability of 80% is reached for missions over 100 000 h in the commercial flights altitude, while for the single transistor system, this value is reached for missions under 100 h.
dc.description.firstpage393
dc.description.issuenumber2
dc.description.lastpage401
dc.description.volume19
dc.identifier.citationPERIN, ANDRE L.; PEREIRA, ARIANNE S. N.; BUHLER, RUDOLF T.; DA SILVEIRA, MARCILEI A. G.; GIACOMINI, RENATO C.. SOI Stacked Transistors Tolerance to Single-Event Effects. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, v. 19, p. 393-401, 2019.
dc.identifier.doi10.1109/TDMR.2019.2912862
dc.identifier.issn1558-2574
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1297
dc.relation.ispartofIEEE Transactions on Device and Materials Reliability
dc.rightsAcesso Restrito
dc.subject.otherlanguageModeling
dc.subject.otherlanguageradiation hardening (electronics)
dc.subject.otherlanguagesemiconductor device reliability
dc.subject.otherlanguagesingle event effects (SEE)
dc.titleSOI Stacked Transistors Tolerance to Single-Event Effects
dc.typeArtigo
fei.scopus.citations2
fei.scopus.eid2-s2.0-85065147811
fei.scopus.subjectIntegrated circuit modeling
fei.scopus.subjectIntegrated circuit reliability
fei.scopus.subjectMOS-FET
fei.scopus.subjectRadiation hardening (electronics)
fei.scopus.subjectSemiconductor device reliability
fei.scopus.subjectSingle event effects
fei.scopus.updated2023-12-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85065147811&origin=inward
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