Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment

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dc.contributor.authorGALEMBECK, E. H.S.
dc.contributor.authorRENAUX, C.
dc.contributor.authorFLANDRE, D.
dc.contributor.authorFINCO, S.
dc.contributor.authorSalvador Gimenez
dc.date.accessioned2022-01-12T21:58:12Z
dc.date.available2022-01-12T21:58:12Z
dc.date.issued2017-03-05
dc.description.abstractThis paper describes an experimental comparative study between the silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field effect transistors (MOSFETs) implemented with the octagonal gate geometries and their typical rectangular counterparts operating in high-temperature conditions. The 1 m fully depleted SOI complementary metal-oxide semiconductor technology was employed to manufacture the devices. We observe that the octagonal layout style for MOSFETs is capable of maintaining its better electrical performance (for 573 K: a reduction of the leakage drain current of 65%, an increase of 159% in the saturation drain current, and an increase of 175% in the unit voltage gain frequency) in comparison to the standard rectangular counterpart. This happens because the longitudinal corner effect and parallel connection of MOSFETs with different channel lengths effect continue to function at high temperatures. Therefore, the octagonal layout style can be considered as an alternative hardness-by-design approach to boost the electrical performance of n-type SOI MOSFETs in high-temperature environments, without causing any extra burden for any current planar SOI MOSFET manufacturing process.
dc.description.firstpage221
dc.description.issuenumber1
dc.description.lastpage228
dc.description.volume17
dc.identifier.citationGALEMBECK, E. H.S.; RENAUX, C.; FLANDRE, D.; FINCO, S.; GIMENEZ, S. Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment. IEEE Transactions on Device and Materials Reliability, v. 17, n. 1, p. 221-228, Marc, 2017.
dc.identifier.doi10.1109/TDMR.2017.2652729
dc.identifier.issn1558-2574
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3846
dc.relation.ispartofIEEE Transactions on Device and Materials Reliability
dc.rightsAcesso Restrito
dc.subject.otherlanguagehigh-temperature environment
dc.subject.otherlanguageLCE effect and PAMDLE effect
dc.subject.otherlanguageOCTO layout style
dc.titleBoosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment
dc.typeArtigo
fei.scopus.citations9
fei.scopus.eid2-s2.0-85017587917
fei.scopus.subjectComplementary metal-oxide-semiconductor technologies
fei.scopus.subjectHigh temperature condition
fei.scopus.subjectHigh-temperature environment
fei.scopus.subjectLCE effect and PAMDLE effect
fei.scopus.subjectMetal oxide semiconductor
fei.scopus.subjectOCTO layout style
fei.scopus.subjectSaturation drain current
fei.scopus.subjectSilicon-on- insulators (SOI)
fei.scopus.updated2023-11-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85017587917&origin=inward
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