TCAD Evaluation of the Active Substrate Bias Effect on the Charge Transport of Ω-Gate Nanowire MOS Transistors with Ultra-Thin BOX

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dc.contributor.authorBERGAMASHI, F. E.
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.date.accessioned2022-03-01T06:05:03Z
dc.date.available2022-03-01T06:05:03Z
dc.date.issued2022-01-05
dc.description.abstractAuthorThis work presents an analysis of the application of active substrate bias (or back bias) on the charge transport properties of n-type Ω-gate SOI nanowire MOS transistors with thin buried oxide (BOX) and variable fin width. Additionally, the influence of back bias on the electrical parameters of these devices is also investigated through DC parameters such as on-to-off-state current ratio and DIBL. The evaluation is conducted by 3D TCAD simulations calibrated with experimental data. The application of negative back bias on nMOS transistors not only shifts the threshold voltage, but also causes mobility degradation due to the negative potential on the channel pushing the charges against the gate oxide interface. On the other hand, when positive back bias is applied, despite the mobility improvement allowed by the back channel’s superior mobility and the front channel’s less compacted inversion layer, at higher substrate bias levels, a strong mobility degradation is observed in the back channel due to the substrate’s high electric field, resulting in reduction of the channel’s overall effective mobility. The application of positive substrate bias degrades the subthreshold slope, leading to smaller on-to-off-state current ratio, as well as the reduced control of channel charges by the gate electrode worsens the DIBL.
dc.description.firstpage1
dc.description.lastpage7
dc.identifier.citationBERGAMASHI, F. E.; PAVANELLO, M. A. TCAD Evaluation of the Active Substrate Bias Effect on the Charge Transport of Ω-Gate Nanowire MOS Transistors with Ultra-Thin BOX. IEEE Journal of the Electron Devices Society, p. 1-7, 2022.
dc.identifier.doi10.1109/JEDS.2022.3144028
dc.identifier.issn2168-6734
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4426
dc.relation.ispartofIEEE Journal of the Electron Devices Society
dc.rightsAcesso Aberto
dc.rights.licenseCreative Commons "Este é um artigo publicado em acesso aberto sob uma licença Creative commons (CC BY 4.0). Fonte: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85123387060&origin=inward. Acesso em: 08 mar. 2022.
dc.subject.otherlanguageDegradation
dc.subject.otherlanguageLogic gates
dc.subject.otherlanguageMobility
dc.subject.otherlanguageNanoscale devices
dc.subject.otherlanguageNanowire MOS transistors
dc.subject.otherlanguagePerformance evaluation
dc.subject.otherlanguageSubstrate bias
dc.subject.otherlanguageSubstrates
dc.subject.otherlanguageThin BOX.
dc.subject.otherlanguageThreshold voltage
dc.subject.otherlanguageTransistors
dc.titleTCAD Evaluation of the Active Substrate Bias Effect on the Charge Transport of Ω-Gate Nanowire MOS Transistors with Ultra-Thin BOX
dc.typeArtigo
fei.scopus.citations0
fei.scopus.eid2-s2.0-85123387060
fei.scopus.subjectActive substrates
fei.scopus.subjectBack bias
fei.scopus.subjectBuried oxides
fei.scopus.subjectMobility
fei.scopus.subjectNanoscale device
fei.scopus.subjectNanowire MOS transistor
fei.scopus.subjectOff-state current
fei.scopus.subjectPerformances evaluation
fei.scopus.subjectSubstrate bias
fei.scopus.subjectThin buried oxide.
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85123387060&origin=inward
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