Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors

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dc.contributor.authorTREVISOLI, RENAN
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorCAPOVILLA, CARLOS EDUARDO
dc.contributor.authorBARRAUD, SYLVAIN
dc.contributor.authorDORIA, RODRIGO TREVISOLI
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.date.accessioned2021-11-09T17:37:48Z
dc.date.available2021-11-09T17:37:48Z
dc.date.issued2020-04-24
dc.description.abstractThis article aims at proposing a compact analytical model for the low-frequency noise (LFN) of junctionless nanowire transistors (JNTs), operating at different bias conditions and temperatures. The model is validated through tridimensional numerical simulations, accounting for different trap configurations, as well as devices with different channel lengths, nanowire widths, and doping concentrations. Experimental results of short-channel junctionless transistors have also been used to demonstrate the model's applicability and accuracy.
dc.description.firstpage2536
dc.description.lastpage2543
dc.description.volume67
dc.identifier.citationTREVISOLI, R D; PAVANELLO, M. A.; CAPOVILLA, C. E.; BARRAUD, S.; DORIA, R. T. Analytical model for Low-Frequency noise in junctionless nanowire transistors. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 67, p. 2536-2543, 2020.
dc.identifier.doi10.1109/TED.2020.2986141
dc.identifier.issn0018-9383
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3451
dc.relation.ispartofIEEE TRANSACTIONS ON ELECTRON DEVICES
dc.rightsAcesso Restrito
dc.subjectanalytical model
dc.subjectinterface traps
dc.subjectjunctionless
dc.subjectlow-frequency noise (LFN)
dc.subjectnanowires
dc.titleAnalytical Model for Low-Frequency Noise in Junctionless Nanowire Transistorspt_BR
dc.typeArtigopt_BR
fei.scopus.citations6
fei.scopus.eid2-s2.0-85085554308
fei.scopus.updated2024-03-04
fei.source.urlhttps://ieeexplore.ieee.org/document/9078354
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