Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

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dc.contributor.authorPaz B.C.
dc.contributor.authorCasse M.
dc.contributor.authorBarraud S.
dc.contributor.authorReimbold G.
dc.contributor.authorVinet M.
dc.contributor.authorFaynot O.
dc.contributor.authorPavanello M.A.
dc.date.accessioned2019-08-19T23:45:13Z
dc.date.available2019-08-19T23:45:13Z
dc.date.issued2018
dc.description.abstract© 2018 Elsevier LtdThis work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate level. The proposed methodology is based on experimental measurements of the total drain current (IDS) varying the back gate bias (VB), aiming the extraction of carriers’ mobility of each level separately. The methodology consists of three main steps and accounts for VB influence on mobility. The behavior of non-stacked Ω-gate NWs are also discussed varying VB through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on VB for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Ω-gate. The procedure was validated for a wide range of VB and up to 150 °C. Similar temperature dependence of mobility was observed for both Ω-gate and GAA levels.
dc.description.firstpage62
dc.description.issuenumber11
dc.description.lastpage70
dc.description.volume149
dc.identifier.citationCARDOSO PAZ, BRUNA; CASSÉ, MIKAËL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; ANTONIO PAVANELLO, MARCELO. Methodology to Separate Channel Conductions of Two Level Vertically Stacked SOI Nanowire MOSFETs. SOLID-STATE ELECTRONICS, v. 149, n. 11, p. 62-70, 2018.
dc.identifier.doi10.1016/j.sse.2018.08.012
dc.identifier.issn0038-1101
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1135
dc.relation.ispartofSolid-State Electronics
dc.rightsAcesso Restrito
dc.subject.otherlanguageBack gate bias
dc.subject.otherlanguageMobility
dc.subject.otherlanguageSOI
dc.subject.otherlanguageTemperature
dc.subject.otherlanguageTridimensional numerical simulations
dc.subject.otherlanguageVertically stacked nanowires
dc.titleMethodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs
dc.typeArtigo
fei.scopus.citations0
fei.scopus.eid2-s2.0-85052893965
fei.scopus.subjectBack-gate bias
fei.scopus.subjectChannel conduction
fei.scopus.subjectInversion modes
fei.scopus.subjectMobility dependences
fei.scopus.subjectNanowire MOSFETs
fei.scopus.subjectNanowires (NWs)
fei.scopus.subjectStacked structure
fei.scopus.subjectTemperature dependence
fei.scopus.updated2024-12-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85052893965&origin=inward
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