A novel processor architecture with a hardware microkernel to improve the performance of task-based systems

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dc.contributor.authorDANTAS, L. P.
dc.contributor.authorDE AZEVEDO, R. J.
dc.contributor.authorSalvador Gimenez
dc.contributor.authorOrcidhttps://orcid.org/0000-0002-3616-9559
dc.date.accessioned2022-01-12T21:56:25Z
dc.date.available2022-01-12T21:56:25Z
dc.date.issued2019-06-05
dc.description.abstract© 2018 IEEE.The use of hardware to perform part of central processing unit (CPU) processing functions is a consolidated practice that produces good results in terms of power and performance when applied in embedded systems. This letter describes the changes in the processor architecture to embed the functions of a microkernel to boost the performance of task-based systems. Part of the CPU overhead is caused by the microkernel to run the scheduler algorithm and context switching. Therefore, the microkernel's functions, supported by a single additional internal register bank, were implemented by hardware to work in parallel with the CPU to reduce the task dispatch time. The experimental results show that by using this approach, the performance is virtually independent of the time slice, whereas the conventional approach (software implementation) is degraded by 79% as the time slice decreases.
dc.description.firstpage46
dc.description.issuenumber2
dc.description.lastpage49
dc.description.volume11
dc.identifier.citationDANTAS, L. P. ; DE AZEVEDO, R. J.; GIMENEZ, S. A novel processor architecture with a hardware microkernel to improve the performance of task-based systems. IEEE Embedded Systems Letters, v. 11, n. 2, p. 46-49, Jun. 2019.
dc.identifier.doi10.1109/LES.2018.2864094
dc.identifier.issn1943-0663
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3723
dc.relation.ispartofIEEE Embedded Systems Letters
dc.rightsAcesso Restrito
dc.subject.otherlanguageHardware microkernel
dc.subject.otherlanguageprocessor architecture
dc.subject.otherlanguagereal-time system
dc.subject.otherlanguageshort time slice
dc.subject.otherlanguagetask-based system (TBS)
dc.titleA novel processor architecture with a hardware microkernel to improve the performance of task-based systems
dc.typeArtigo
fei.scopus.citations4
fei.scopus.eid2-s2.0-85051374809
fei.scopus.subjectContext
fei.scopus.subjectMicrokernel
fei.scopus.subjectProcessor architectures
fei.scopus.subjectRegisters
fei.scopus.subjectTask analysis
fei.scopus.subjectTask-based
fei.scopus.subjectTime slice
fei.scopus.updated2023-11-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85051374809&origin=inward
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