Analytical model for potential in double-gate juntionless transistors
dc.contributor.author | CERDEIRA, A. | |
dc.contributor.author | ESTRADA, M. | |
dc.contributor.author | TREVISOLI, R. D. | |
dc.contributor.author | Rodrido Doria | |
dc.contributor.author | Michelly De Souza | |
dc.contributor.author | Marcelo Antonio Pavanello | |
dc.contributor.authorOrcid | https://orcid.org/0000-0003-4448-4337 | |
dc.contributor.authorOrcid | https://orcid.org/0000-0001-6472-4807 | |
dc.contributor.authorOrcid | https://orcid.org/0000-0003-1361-3650 | |
dc.date.accessioned | 2022-01-12T22:01:53Z | |
dc.date.available | 2022-01-12T22:01:53Z | |
dc.date.issued | 2013-09-06 | |
dc.description.abstract | An analytical model to calculate the potential at the surface and at the center of silicon layer for long-channel Junctionless transistors is derived and explained the basic details. The analytical model is compared with the numerical solution of the fundamental equations showing the validity of the assumptions considered. © 2013 IEEE. | |
dc.identifier.citation | CERDEIRA, A.; ESTRADA, M.; TREVISOLI, R. D.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A. Analytical model for potential in double-gate juntionless transistors. Chip in Curitiba 2013 - SBMicro 2013: 28th Symposium on Microelectronics Technology and Devices. Sept. 2013. | |
dc.identifier.doi | 10.1109/SBMicro.2013.6676165 | |
dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/4097 | |
dc.relation.ispartof | Chip in Curitiba 2013 - SBMicro 2013: 28th Symposium on Microelectronics Technology and Devices | |
dc.rights | Acesso Restrito | |
dc.subject.otherlanguage | Analytical calculation of potentials | |
dc.subject.otherlanguage | Junctionless transistors | |
dc.title | Analytical model for potential in double-gate juntionless transistors | |
dc.type | Artigo de evento | |
fei.scopus.citations | 2 | |
fei.scopus.eid | 2-s2.0-84893460089 | |
fei.scopus.subject | Analytical calculation | |
fei.scopus.subject | Double-gate | |
fei.scopus.subject | Fundamental equations | |
fei.scopus.subject | Junctionless transistors | |
fei.scopus.subject | Numerical solution | |
fei.scopus.subject | Silicon layer | |
fei.scopus.updated | 2025-02-01 | |
fei.scopus.url | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84893460089&origin=inward |