Fpga implementation of asynchronous controllers from generalized multi-burst graph specification

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dc.contributor.authorOLIVEIRA, D. L.
dc.contributor.authorFERREIRA, L. S.
dc.contributor.authorROMANO, L.
dc.date.accessioned2022-01-12T22:03:55Z
dc.date.available2022-01-12T22:03:55Z
dc.date.issued2010-09-14
dc.description.abstractFPGAs have been mainly used for designing of synchronous controllers. However, it is difficult to design asynchronous controllers on them because the circuit may suffer from hazard problems. This paper presents a method that implements a class of asynchronous controllers on FPGAs which are based on Look-Up Table (LUT) architectures. Asynchronous controllers specification used in heterogeneous (synchronous +asynchronous) systems rely on two types of signals: level sensitive signals that are used as conditionals and transition sensitive signals. Another requirement is to describe concurrency between inputs/outputs. The Multi-Burst Graph (MBG) specification allows to described these controllers in a compact form and also the MBG specification is familiar to the designers of digital circuits. This paper also proposes a generalization in the MBG specification to increase the ability to describe the interaction between inputs/ outputs. Our method begins from Generalized MBG specification. By doing this, the asynchronous circuits besides their intrinsic advantages over synchronous ones may also take advantage of integration, lower costs and shorttime design associated with FPGA designs. ©2010 IEEE.
dc.identifier.citationOLIVEIRA, D. L.; FERREIRA, L. S.; ROMANO, L. Fpga implementation of asynchronous controllers from generalized multi-burst graph specification. 2010 IEEE ANDESCON Conference Proceedings, ANDESCON 2010,
dc.identifier.doi10.1109/ANDESCON.2010.5633258
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4236
dc.relation.ispartof2010 IEEE ANDESCON Conference Proceedings, ANDESCON 2010
dc.rightsAcesso Restrito
dc.subject.otherlanguageAsynchronous logic
dc.subject.otherlanguageBurst-mode
dc.subject.otherlanguageComponent
dc.subject.otherlanguageFPGA
dc.subject.otherlanguageHazard
dc.subject.otherlanguageMulti-burst graph
dc.subject.otherlanguageSynthesis
dc.subject.otherlanguageXBM
dc.titleFpga implementation of asynchronous controllers from generalized multi-burst graph specification
dc.typeArtigo de evento
fei.scopus.citations0
fei.scopus.eid2-s2.0-79952077277
fei.scopus.subjectAsynchronous logic
fei.scopus.subjectBurst-mode
fei.scopus.subjectComponent
fei.scopus.subjectFPGA
fei.scopus.subjectMulti-burst graph
fei.scopus.subjectSynthesis
fei.scopus.subjectXBM
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=79952077277&origin=inward
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