Analysis of Current Mirrors with Asymmetric Self-Cascode Association of SOI MOSFETs through SPICE Simulations

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dc.contributor.authorSILVA, PAULO RODRIGUES
dc.contributor.authorMichelly De Souza
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-6472-4807
dc.date.accessioned2021-11-11T18:02:12Z
dc.date.available2021-11-11T18:02:12Z
dc.date.issued2020-07-31
dc.description.firstpage1
dc.description.issuenumber2
dc.description.lastpage5
dc.description.volume15
dc.identifier.citationSILVA, P. R.; SOUZA, M. DE. Analysis of current mirrors with asymmetric Self-Cascode association of SOI MOSFETs through SPICE simulations. JICS. Journal of Integrated Circuits And Systems (ED. PORTUGUÊS), v. 15, n. 2, p. 1-5, 2020.
dc.identifier.doi10.29292/jics.v15i2.159
dc.identifier.issn1807-1953
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3459
dc.relation.ispartofJICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS)
dc.rightsAcesso Aberto
dc.rights.licenseCreative Commons "Este é um artigo publicado em acesso aberto sob uma licença Creative Commons (CC BY-NC-ND 4.0). Fonte: https://jics.org.br/ojs/index.php/JICS/article/view/159. Acesso em: 11 nov. 2021.
dc.subjectSOI nMOSFET transistor
dc.subjectAsymmetric self-cascode
dc.subjectComposite transistor
dc.subjectCurrent Mirror
dc.subjectSPICE Simulation
dc.subjectRobotics
dc.titleAnalysis of Current Mirrors with Asymmetric Self-Cascode Association of SOI MOSFETs through SPICE Simulationspt_BR
dc.typeArtigopt_BR
dcterms.abstractIn this paper the performance of different architectures of current mirrors implemented with single SOI transistors and self-cascode transistors, both symmetric and asymmetric is evaluated. A comparison of current mirrors figures of merit, looking for the advantages of the asymmetric composite structure in relation to a single SOI MOSFETs and the symmetric self-cascode transistor is performed. This analysis has been carried out through analytical simulations, using common-source, Cascode and Wilson current mirrors architectures. It is shown that asymmetric configuration can provide larger output resistance even in the common-source current mirror than other architectures with conventional single transistors.
fei.scopus.citations0
fei.scopus.eid2-s2.0-85090604995
fei.scopus.updated2024-03-04
fei.source.urlhttps://jics.org.br/ojs/index.php/JICS/article/view/159
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