Evaluation of Analog Characteristics of n-Type Vertically Stacked Nanowires
dc.contributor.author | MARINELLO, GENARO | |
dc.contributor.author | BARRAUD, SYLVAIN | |
dc.contributor.author | VINET, MAUD | |
dc.contributor.author | FAYNOT, OLIVIER | |
dc.contributor.author | PAZ, BRUNA CARDOSO | |
dc.contributor.author | Marcelo Antonio Pavanello | |
dc.contributor.authorOrcid | https://orcid.org/0000-0003-1361-3650 | |
dc.date.accessioned | 2022-01-12T21:54:55Z | |
dc.date.available | 2022-01-12T21:54:55Z | |
dc.date.issued | 2020-09-01 | |
dc.description.abstract | This paper aims at analyzing the analog characteristics of n-type vertically stacked nanowires with 2 channels, varying the fin width and channel length. The basic electrical parameters such as threshold voltage and subthreshold slope are extracted in the linear region, whereas the transconductance, output conductance, and intrinsic voltage gain are extracted in saturation. | |
dc.identifier.citation | MARINELLO, G.; BARRAUD, S.; VINET, M.; FAYNOT, O.; PAZ, B. C.; PAVANELLO, M. A. Evaluation of analog characteristics of n-Type vertically stacked nanowires. 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020. | |
dc.identifier.doi | 10.1109/EUROSOI-ULIS49407.2020.9365636 | |
dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/3626 | |
dc.relation.ispartof | 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020 | |
dc.rights | Acesso Restrito | |
dc.subject.otherlanguage | Analog | |
dc.subject.otherlanguage | MOSFET | |
dc.subject.otherlanguage | Nanowire | |
dc.subject.otherlanguage | Stacked | |
dc.title | Evaluation of Analog Characteristics of n-Type Vertically Stacked Nanowires | |
dc.type | Artigo de evento | |
fei.scopus.citations | 1 | |
fei.scopus.eid | 2-s2.0-85102972096 | |
fei.scopus.subject | Channel length | |
fei.scopus.subject | Electrical parameter | |
fei.scopus.subject | Fin widths | |
fei.scopus.subject | Intrinsic voltage gains | |
fei.scopus.subject | Linear region | |
fei.scopus.subject | Output conductance | |
fei.scopus.subject | Subthreshold slope | |
fei.scopus.updated | 2024-08-01 | |
fei.scopus.url | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85102972096&origin=inward |