Influence of non-vertical sidewall on finfet threshold voltage

Abstract

The FinFET structure is one of the most promising architecture approaches to double-gate devices. Due to limitations of process uniformity, most fabricated FinFETs have width variation along the vertical direction, resulting in non-vertical sidewalls. The impact of non-vertical sidewalls on the threshold voltage of FinFETs is studied in this work through three-dimensional simulation. The main purpose of this study is to verify the applicability of some analytical models developed to double-gate devices with parallel gates to FinFETs with inclined sidewalls. The behavior of the threshold voltage for different doping levels and silicon film width is discussed. The use of the existing models taking an average width of the silicon film as the device width is proposed and shows to be a good approximation. © 2006 The Electrochemical Society.