Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors

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dc.contributor.authorTREVISOLI, Renan D.
dc.contributor.authorDORIA, Rodrigo Trevisoli
dc.contributor.authorDE SOUZA, MICHELLY
dc.contributor.authorPAVANELLO, Marcelo Antonio
dc.date.accessioned2019-08-19T23:45:16Z
dc.date.available2019-08-19T23:45:16Z
dc.date.issued2013
dc.description.firstpage116
dc.description.issuenumber2
dc.description.lastpage124
dc.description.volume8
dc.identifier.citationTREVISOLI, Renan D.; DORIA, Rodrigo Trevisoli; DE SOUZA, MICHELLY; PAVANELLO, Marcelo Antonio. Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors. JICS. Journal of Integrated Circuits and Systems (Ed. Português), v. 8, n. 2, p. 116-124, 2013.
dc.identifier.issn1807-1953
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1178
dc.relation.ispartofJICS. Journal of Integrated Circuits and Systems (Ed. Português)
dc.rightsAcesso Restrito
dc.titleDrain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistorspt_BR
dc.typeArtigopt_BR
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