Application of the symmetric doped double-gate model in circuit simulation containing double-gate graded-channel transistors

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dc.contributor.authorCONTRERAS, E.
dc.contributor.authorCERDEIRA, A.
dc.contributor.authorALVARADO J.
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.date.accessioned2022-01-12T22:04:27Z
dc.date.available2022-01-12T22:04:27Z
dc.date.issued2009-09-03
dc.description.abstractThe development of models to simulate circuits containing new devices is an important task to allow for the introduction of these devices in practical applications. In this paper we show the advantages of using the Symmetric Doped Double-Gate Model recently developed and are already introduced in SmartSpice simulator, for modeling circuits containing Double-Gate Graded-Channel (GC) transistors. In this case there is no need to use two different models to represent the graded-channel device, as has been done up to now. A current-mirror circuit using GC devices has been simulated and the results were validated comparing them with those obtained in MIXED-MODE and two-dimensional ATLAS simulation of the GC devices. © The Electrochemical Society.
dc.description.firstpage597
dc.description.issuenumber1
dc.description.lastpage604
dc.description.volume23
dc.identifier.citationCONTRERAS, E.; CERDEIRA, A.; ALVARADO J.; PAVANELLO, M. A. Application of the symmetric doped double-gate model in circuit simulation containing double-gate graded-channel transistors. ECS Transactions, v. 23, n. 1, p. 597-604, Sept. 2009.
dc.identifier.doi10.1149/1.3183769
dc.identifier.issn1938-5862
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4272
dc.relation.ispartofECS Transactions
dc.rightsAcesso Restrito
dc.titleApplication of the symmetric doped double-gate model in circuit simulation containing double-gate graded-channel transistors
dc.typeArtigo de evento
fei.scopus.citations3
fei.scopus.eid2-s2.0-74549203960
fei.scopus.subjectATLAS simulations
fei.scopus.subjectChannel device
fei.scopus.subjectChannel transistors
fei.scopus.subjectCurrent-mirror circuits
fei.scopus.subjectDouble-gate
fei.scopus.subjectMixed mode
fei.scopus.subjectNew devices
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=74549203960&origin=inward
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