Low subthreshold slope in junctionless multigate transistors

Página do item simplificado
dc.contributor.authorLee, Chi-Woo
dc.contributor.authorNazarov, Alexei N.
dc.contributor.authorFerain, Isabelle
dc.contributor.authorAkhavan, Nima Dehdashti
dc.contributor.authorYan, Ran
dc.contributor.authorRazavi, Pedram
dc.contributor.authorYu, Ran
dc.contributor.authorDoria, Rodrigo T.
dc.contributor.authorColinge, Jean-Pierre
dc.date.accessioned2019-08-19T23:45:26Z
dc.date.available2019-08-19T23:45:26Z
dc.date.issued2010
dc.description.firstpage102106
dc.description.volume96
dc.identifier.citationLee, Chi-Woo; Nazarov, Alexei N.; Ferain, Isabelle; Akhavan, Nima Dehdashti; Yan, Ran; Razavi, Pedram; Yu, Ran; Doria, Rodrigo T.; Colinge, Jean-Pierre. Low subthreshold slope in junctionless multigate transistors. Applied Physics Letters, v. 96, p. 102106, 2010.
dc.identifier.doi10.1063/1.3358131
dc.identifier.issn0003-6951
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1284
dc.relation.ispartofApplied Physics Letters
dc.rightsAcesso Restrito
dc.titleLow subthreshold slope in junctionless multigate transistorspt_BR
dc.typeArtigopt_BR
fei.scopus.citations222
fei.scopus.eid2-s2.0-77949665564
fei.scopus.updated2024-03-04
Arquivos
Coleções
Artigos