Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K

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dc.contributor.authorPaz B.C.
dc.contributor.authorDoria R.T.
dc.contributor.authorCasse M.
dc.contributor.authorBarraud S.
dc.contributor.authorReimbold G.
dc.contributor.authorVinet M.
dc.contributor.authorFaynot O.
dc.contributor.authorPavanello M.A.
dc.date.accessioned2019-08-19T23:45:13Z
dc.date.available2019-08-19T23:45:13Z
dc.date.issued2017
dc.description.abstract© 2017 Elsevier LtdThe linearity of triple gate nanowire transistors (NWs) implemented on a Silicon-On-Insulator (SOI) substrate is investigated in this work considering temperature (T) influence. The analysis is performed in long channel nanowire MOSFETs with different fin width (WFIN), from quasi-planar structures (WFIN = 10 μm) to narrow devices (9.5 nm), operating as single-transistor amplifiers from room temperature down to 100 K. The total, second and third order harmonic distortions (THD, HD2 and HD3, respectively) are extracted using the Integral Function Method (IFM). The analysis is divided in two parts. First, a fixed input signal is applied at the gate of the single-transistor amplifiers and, then, the output signal is fixed. Transport parameters such as effective mobility (μeff), mobility degradation coefficient (θ) and series resistance (RS) have been extracted down to 100 K and correlated to the distortion to explain linearity peaks behavior with temperature and fin width. Narrow transistors have shown improved linearity mainly due to higher intrinsic voltage gain (AV) considering the entire temperature range. Low temperature operation has shown to degrade the linearity characteristics of both wide and narrow NW MOSFETs.
dc.description.firstpage111
dc.description.lastpage118
dc.description.volume79
dc.identifier.citationPAZ, Bruna Cardoso; Doria, Rodrigo Trevisoli; CASSÉ, MIKAËL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; Pavanello, Marcelo Antonio. Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K. MICROELECTRONICS RELIABILITY, v. 79, p. 111-118, 2017.
dc.identifier.doi10.1016/j.microrel.2017.10.008
dc.identifier.issn0026-2714
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1131
dc.relation.ispartofMicroelectronics Reliability
dc.rightsAcesso Restrito
dc.subject.otherlanguageHarmonic distortion
dc.subject.otherlanguageLow temperature
dc.subject.otherlanguageNanowires
dc.subject.otherlanguageSOI MOSFETs
dc.subject.otherlanguageTriple gate
dc.titleHarmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K
dc.typeArtigo
fei.scopus.citations1
fei.scopus.eid2-s2.0-85034816140
fei.scopus.subjectHarmonic distortion analysis
fei.scopus.subjectIntegral function method
fei.scopus.subjectIntrinsic voltage gains
fei.scopus.subjectLow temperatures
fei.scopus.subjectQuasi-planar structure
fei.scopus.subjectSilicon-on-insulator substrates
fei.scopus.subjectSOI-MOSFETs
fei.scopus.subjectTriple-gate
fei.scopus.updated2024-03-04
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85034816140&origin=inward
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