Synthesis of synchronous digital systems operating in double-edge of clock

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dc.contributor.authorOLIVEIRA, D. L.
dc.contributor.authorCURTINHAS, T.
dc.contributor.authorBOMPEAN, D.
dc.contributor.authorFERREIRA, L. S.
dc.contributor.authorROMANO, L.
dc.date.accessioned2022-01-12T22:02:36Z
dc.date.available2022-01-12T22:02:36Z
dc.date.issued2012-02-05
dc.description.abstractIn a synchronous digital system the activity of the clock signal is a major consumer of energy. It consumes 15% to 45% of energy consumed. Reducing the activity of the clock signal produces a reduction of energy considered, but also reduces clock skew problems and iteration electromagnetic. An interesting strategy is the synchronous digital system to operate in the transitions of both edges of the clock signal (double-edge triggered - DET), as this allows a 50% reduction in the frequency of the clock signal, but having the same processing rate data. In this paper we propose a method for synthesis of synchronous digital systems that operate on both edges of the clock signal, but the state memory is composed only of flip-flops that are sensitive to a single edge of the clock signal (single-edge triggered flip-flops - SET-FF). © 2012 IEEE.
dc.identifier.citationOLIVEIRA, D. L.; CURTINHAS, T.; BOMPEAN, D.; FERREIRA, L. S.; ROMANO, L. Synthesis of synchronous digital systems operating in double-edge of clock. 2012 IEEE 3rd Latin American Symposium on Circuits and Systems, LASCAS 2012 - Conference Proceedings, 2012.
dc.identifier.doi10.1109/LASCAS.2012.6180347
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4146
dc.relation.ispartof2012 IEEE 3rd Latin American Symposium on Circuits and Systems, LASCAS 2012 - Conference Proceedings
dc.rightsAcesso Restrito
dc.titleSynthesis of synchronous digital systems operating in double-edge of clock
dc.typeArtigo de evento
fei.scopus.citations2
fei.scopus.eid2-s2.0-84860478456
fei.scopus.subjectClock signal
fei.scopus.subjectClock skews
fei.scopus.subjectProcessing rates
fei.scopus.subjectSynchronous digital system
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84860478456&origin=inward
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