High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs
dc.contributor.advisorOrcid | https://orcid.org/0000-0001-6472-4807 | |
dc.contributor.advisorOrcid | https://orcid.org/0000-0003-1361-3650 | |
dc.contributor.author | Michelly De Souza | |
dc.contributor.author | CERDEIRA, A. | |
dc.contributor.author | ESTRADA, M. | |
dc.contributor.author | BARRAUD, S. | |
dc.contributor.author | CASSE, M. | |
dc.contributor.author | VINET, M. | |
dc.contributor.author | FAYNOT, O. | |
dc.contributor.author | Pavanello M. A. | |
dc.date.accessioned | 2023-05-01T06:02:51Z | |
dc.date.available | 2023-05-01T06:02:51Z | |
dc.date.issued | 2023-01-05 | |
dc.description.abstract | AuthorIn this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase in device width makes the GIDL current more sensitive to temperature increase. Three-dimensional numerical simulations have shown that despite the reverse junction leakage increase with temperature, leakage current in nanosheet and nanowire transistors is composed predominantly of GIDL current. The change in valence and conduction bands caused by temperature increase favors the band-to-band tunneling, which is responsible for the worsening of GIDL at high temperatures. | |
dc.identifier.citation | DE SOUZA, M.; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; PAVANELLO, M. A. High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs. IEEE Journal of the Electron Devices Society, p. 1-8, 2023. | |
dc.identifier.doi | 10.1109/JEDS.2023.3264876 | |
dc.identifier.issn | 2168-6734 | |
dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/4770 | |
dc.relation.ispartof | IEEE Journal of the Electron Devices Society | |
dc.rights | Acesso Aberto | |
dc.subject.otherlanguage | Current measurement | |
dc.subject.otherlanguage | GIDL | |
dc.subject.otherlanguage | high temperature | |
dc.subject.otherlanguage | Logic gates | |
dc.subject.otherlanguage | Nanoscale devices | |
dc.subject.otherlanguage | nanosheet MOSFET | |
dc.subject.otherlanguage | nanowire MOSFET | |
dc.subject.otherlanguage | SOI | |
dc.subject.otherlanguage | Temperature measurement | |
dc.subject.otherlanguage | Threshold voltage | |
dc.subject.otherlanguage | Transistors | |
dc.subject.otherlanguage | Voltage measurement | |
dc.title | High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs | |
dc.type | Artigo | |
fei.scopus.citations | 5 | |
fei.scopus.eid | 2-s2.0-85153384510 | |
fei.scopus.subject | Drain leakage | |
fei.scopus.subject | Drain leakage current | |
fei.scopus.subject | Gate-induce drain leakage | |
fei.scopus.subject | Highest temperature | |
fei.scopus.subject | MOSFETs | |
fei.scopus.subject | Nanoscale device | |
fei.scopus.subject | Nanosheet MOSFET | |
fei.scopus.subject | Nanowire MOSFETs | |
fei.scopus.subject | SOI | |
fei.scopus.subject | Temperature increase | |
fei.scopus.updated | 2025-02-01 | |
fei.scopus.url | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85153384510&origin=inward |
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