Reliability-Performance Analysis of Hardware and Software Co-Designs in SRAM-Based APSoCs

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dc.contributor.authorTambara L.A.
dc.contributor.authorKastensmidt F.L.
dc.contributor.authorRech P.
dc.contributor.authorLins F.
dc.contributor.authorMedina N.H.
dc.contributor.authorAdded N.
dc.contributor.authorAguiar V.A.P.
dc.contributor.authorSilveira M.A.G.
dc.date.accessioned2019-08-19T23:47:20Z
dc.date.available2019-08-19T23:47:20Z
dc.date.issued2018
dc.description.abstract© 1963-2012 IEEE.All programmable system-on-chip (APSoC) devices provide higher system performance and programmable flexibility at lower costs compared to standalone field-programmable gate array devices and processors. Unfortunately, it has been demonstrated that the high complexity and density of APSoCs increase the system's susceptibility to radiation-induced errors. This paper investigates the effects of soft errors on APSoCs at design level through reliability and performance analyses. We explore 28 different hardware and software co-designs varying the workload distribution between hardware and software. We also propose a reliability analysis flow based on fault injection (FI) to estimate the reliability trend of hardware-only and software-only designs and hardware-software co-designs. Results obtained from both radiation experiments and FI campaigns reveal that performance and reliability can be improved up to 117× by offloading the workload of an APSoC-based system to its programmable logic core. We also show that the proposed flow is a precise method to estimate the reliability trend of system designs on APSoCs before radiation experiments.
dc.description.firstpage1935
dc.description.issuenumber8
dc.description.lastpage1942
dc.description.volume65
dc.identifier.citationTAMBARA, LUCAS ANTUNES; KASTENSMIDT, FERNANDA LIMA; RECH, PAOLO; LINS, FILIPE; MEDINA, NILBERTO H.; ADDED, NEMITALA; AGUIAR, VITOR A. P.; SILVEIRA, MARCILEI A. G.. Reliability-Performance Analysis of Hardware and Software Co-Designs in SRAM-based APSoCs. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, v. 65, n. 8, p. 1935-1942, 2018.
dc.identifier.doi10.1109/TNS.2018.2844250
dc.identifier.issn0018-9499
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1475
dc.relation.ispartofIEEE Transactions on Nuclear Science
dc.rightsAcesso Restrito
dc.subject.otherlanguageAll programmable system-on-chip (APSoC)
dc.subject.otherlanguagefault injection (FI)
dc.subject.otherlanguagefield-programmable gate array (FPGA)
dc.subject.otherlanguagehardware and software co-design
dc.subject.otherlanguageprocessor
dc.subject.otherlanguagesingle-event effects
dc.subject.otherlanguagesoft errors
dc.titleReliability-Performance Analysis of Hardware and Software Co-Designs in SRAM-Based APSoCs
dc.typeArtigo
fei.scopus.citations5
fei.scopus.eid2-s2.0-85048181418
fei.scopus.subjectAPSoC
fei.scopus.subjectCo-designs
fei.scopus.subjectFault injection
fei.scopus.subjectProcessor
fei.scopus.subjectReliability engineering
fei.scopus.subjectSingle event effects
fei.scopus.subjectSoft error
fei.scopus.updated2025-02-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85048181418&origin=inward
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