Drain current model for short-channel triple gate junctionless nanowire transistors

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dc.contributor.authorPaz B.C.
dc.contributor.authorCasse M.
dc.contributor.authorBarraud S.
dc.contributor.authorReimbold G.
dc.contributor.authorFaynot O.
dc.contributor.authorAvila-Herrera F.
dc.contributor.authorCerdeira A.
dc.contributor.authorPavanello M.A.
dc.date.accessioned2019-08-19T23:45:12Z
dc.date.available2019-08-19T23:45:12Z
dc.date.issued2016
dc.description.abstract© 2016 Elsevier LtdThis work proposes a numerical charge-based new model to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration of a single expression that physically describes the junctionless charge density in both accumulation and depletion regimes of operation, leading to a continuous model in all operational regions. The triple gate structure is modeled from an evolution of a previous model designed for double gate junctionless nanowire transistors (2G JNT). Improvements concerning the capacitance coupling, the internal potential changing while reducing the fin height in nanowire transistors and higher immunity to short-channel effects (SCE) are considered. The model validation is performed through both tridimensional numerical simulation and experimental measurements for long and short-channel devices. Through simulated results, it is verified the agreement of the modeled curves for junctionless transistors with different values of fin height. Comparison between the proposed model and experimental data is performed for 3G JNT advanced structures with channel length down to 15 nm and fin height of 8 nm. Results for 3G JNTs with different values of doping concentration and channel width are also displayed showing a good agreement as well. Moreover, 3G JNT performance is also analyzed and compared in the studied structures by extracting the threshold voltage (VTH), subthreshold slope (S), DIBL and model parameters.
dc.description.firstpage1
dc.description.issuenumber8
dc.description.lastpage10
dc.description.volume63
dc.identifier.citationPAZ, B.C.; CASSÉ, M.; BARRAUD, S.; REIMBOLD, G.; FAYNOT, O.; ÁVILA-HERRERA, F.; CERDEIRA, A.; PAVANELLO, M.A.. Drain current model for short-channel triple gate junctionless nanowire transistors. Microelectronics and Reliability, v. 63, n. 8, p. 1-10, 2016.
dc.identifier.doi10.1016/j.microrel.2016.05.006
dc.identifier.issn0026-2714
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1117
dc.relation.ispartofMicroelectronics Reliability
dc.rightsAcesso Restrito
dc.subject.otherlanguageDrain current modeling
dc.subject.otherlanguageShort channel effects
dc.subject.otherlanguageTriple gate junctionless
dc.titleDrain current model for short-channel triple gate junctionless nanowire transistors
dc.typeArtigo
fei.scopus.citations10
fei.scopus.eid2-s2.0-84991728686
fei.scopus.subjectCapacitance coupling
fei.scopus.subjectDrain current models
fei.scopus.subjectJunctionless transistors
fei.scopus.subjectNanowire transistors
fei.scopus.subjectNumerical integrations
fei.scopus.subjectShort-channel devices
fei.scopus.subjectShort-channel effect
fei.scopus.subjectTriple-gate
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84991728686&origin=inward
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