Analysis of the substrate bias effect on the thermal properties of SOI UTBB transistors

Abstract

This work presents an analysis of the thermal resistance of Ultra-Thin Body and Buried Oxide (UTBB) SOI (Silicon-on-Insulator) MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) under a selected set of back gate biases (Vsub), with and without considering the effect of the ground plane. It has been shown that the thermal resistance increases as the substrate bias is reduced. For negative Vsub, a thicker depletion depth is induced by the back gate, confining the overall current closer to the front gate and increasing its density. A thermal resistance reduction of about 8-9% can be obtained by simply increasing the back bias from -2V up to 2 V.