A novel overlapping circular-gate transistor (O-CGT) and its application to analog design

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dc.contributor.authorDE LIMA, J. A.
dc.contributor.authorSalvador Gimenez
dc.contributor.authorOrcidhttps://orcid.org/0000-0002-3616-9559
dc.date.accessioned2022-01-12T22:04:17Z
dc.date.available2022-01-12T22:04:17Z
dc.date.issued2009-10-02
dc.description.abstractThis paper introduces an Overlapping Circular-Gate Transistor (O-CGT) that allows gate overlaying between neighboring cells, enhancing layout packing with respect to conventional circular- and rectangular-gate structures. Although a section of gate annulus does not contribute to the drain current, a higher aspect-ratio is attained. Besides, both drain and source junctions have their area minimized, so that faster transients can be reached. A first-order model for (W/L)eff of the proposed device is developed and its validity attested by a range of 3D-simulation of IDS x VDS characteristics from ATLAS3D software. Error between analytical and 3Dsimulation data was limited to only 2.9%. With respect to a conventional circular-gate transistor (CGT), the O-CGT breakdown voltage BVDS is reduced by only 6.1%. An O-CGTbased power FET with on-resistance of tens of mO is laid out. An area saving of 18.6% is achieved as compared to rectangular geometries. O-CGT geometries as unit cells to compound a radiation-hardened OTA are also studied.
dc.description.firstpage11
dc.description.lastpage16
dc.identifier.citationDE LIMA, J. A.; GIMENEZ, S. A novel overlapping circular-gate transistor (O-CGT) and its application to analog design. Proceedings of the Argentine School of Micro-Nanoelectronics, Technology and Applications 2009, EAMTA 2009, p. 11-16, Oct. 2009.
dc.identifier.doi10.1109/EAMTA.2009.5288908
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4261
dc.relation.ispartofProceedings of the Argentine School of Micro-Nanoelectronics, Technology and Applications 2009, EAMTA 2009
dc.rightsAcesso Restrito
dc.titleA novel overlapping circular-gate transistor (O-CGT) and its application to analog design
dc.typeArtigo de evento
fei.scopus.citations14
fei.scopus.eid2-s2.0-71949128129
fei.scopus.subject3D simulations
fei.scopus.subjectAnalog design
fei.scopus.subjectArea savings
fei.scopus.subjectBreakdown voltage
fei.scopus.subjectFirst-order models
fei.scopus.subjectGate structure
fei.scopus.subjectGate transistors
fei.scopus.subjectOn-resistance
fei.scopus.subjectPower FETs
fei.scopus.subjectRadiation-hardened
fei.scopus.subjectRectangular geometry
fei.scopus.subjectSource junctions
fei.scopus.subjectUnit cells
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=71949128129&origin=inward
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