Double-gate junctionless transistor model including short-channel effects

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dc.contributor.authorPaz B.C.
dc.contributor.authorAvila-Herrera F.
dc.contributor.authorCerdeira A.
dc.contributor.authorPavanello M.A.
dc.date.accessioned2019-08-19T23:45:11Z
dc.date.available2019-08-19T23:45:11Z
dc.date.issued2015
dc.description.abstract© 2015 IOP Publishing Ltd.This work presents a physically based model for double-gate junctionless transistors (JLTs), continuous in all operation regimes. To describe short-channel transistors, short-channel effects (SCEs), such as increase of the channel potential due to drain bias, carrier velocity saturation and mobility degradation due to vertical and longitudinal electric fields, are included in a previous model developed for long-channel double-gate JLTs. To validate the model, an analysis is made by using three-dimensional numerical simulations performed in a Sentaurus Device Simulator from Synopsys. Different doping concentrations, channel widths and channel lengths are considered in this work. Besides that, the series resistance influence is numerically included and validated for a wide range of source and drain extensions. In order to check if the SCEs are appropriately described, besides drain current, transconductance and output conductance characteristics, the following parameters are analyzed to demonstrate the good agreement between model and simulation and the SCEs occurrence in this technology: threshold voltage (V<inf>TH</inf>), subthreshold slope (S) and drain induced barrier lowering.
dc.description.firstpage1
dc.description.issuenumber5
dc.description.lastpage11
dc.description.volume30
dc.identifier.citationPAZ, Bruna Cardoso; AVILA, FERNANDO; CERDEIRA, Antonio; Pavanello, Marcelo Antonio. Double-gate junctionless transistor model including short-channel effects. Semiconductor Science and Technology, v. 30, p. 055011, 2015.
dc.identifier.doi10.1088/0268-1242/30/5/055011
dc.identifier.issn1361-6641
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1106
dc.relation.ispartofSemiconductor Science and Technology
dc.rightsAcesso Restrito
dc.subject.otherlanguageJunctionless
dc.subject.otherlanguageModel
dc.subject.otherlanguageShort-channel
dc.titleDouble-gate junctionless transistor model including short-channel effects
dc.typeArtigo
fei.scopus.citations24
fei.scopus.eid2-s2.0-84928717099
fei.scopus.subjectCarrier velocity saturation
fei.scopus.subjectDrain-induced barrier lowering
fei.scopus.subjectJunctionless
fei.scopus.subjectPhysically based modeling
fei.scopus.subjectShort channel transistors
fei.scopus.subjectShort channels
fei.scopus.subjectSource and drain extensions
fei.scopus.subjectThree-dimensional numerical simulations
fei.scopus.updated2024-03-04
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84928717099&origin=inward
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