Impact of designer knowledge in the interactive evolutionary optimisation of analogue CMOS ICs by using iMTGSPICE
dc.contributor.author | Moreto R.A.L. | |
dc.contributor.author | Thomaz C.E. | |
dc.contributor.author | Gimenez S.P. | |
dc.date.accessioned | 2019-08-19T23:45:26Z | |
dc.date.available | 2019-08-19T23:45:26Z | |
dc.date.issued | 2019 | |
dc.description.abstract | © The Institution of Engineering and Technology 2019.This Letter describes an innovative interactive evolutionary computational tool to optimise robust analogue complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs), by using genetic algorithm, entitled iMTGSPICE. The main results demonstrate that the iMTGSPICE is able to reduce the optimisation cycle times of designs of robust single-ended single-stage and Miller operational transconductance amplifiers (OTAs) in up to 93.9% in comparison to the non-interactive optimisation process. Moreover, the iMTGSPICE is capable of reducing the influence of the knowledge levels of the analogue CMOS ICs designers (experts and non-experts) to obtain robust potential solutions (maximum error of 0.5% for the Miller OTA). | |
dc.description.firstpage | 16 | |
dc.description.issuenumber | 1 | |
dc.description.lastpage | 18 | |
dc.description.volume | 55 | |
dc.identifier.citation | MORETO, R.A.L.; THOMAZ, C.E.; GIMENEZ, S.P.. Impact of designer knowledge in the interactive evolutionary optimisation of analogue CMOS ICs by using iMTGSPICE. ELECTRONICS LETTERS, v. 55, n. 1, p. 16-18, 2019. | |
dc.identifier.doi | 10.1049/el.2018.6840 | |
dc.identifier.issn | 0013-5194 | |
dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/1280 | |
dc.relation.ispartof | Electronics Letters | |
dc.rights | Acesso Aberto | |
dc.title | Impact of designer knowledge in the interactive evolutionary optimisation of analogue CMOS ICs by using iMTGSPICE | |
dc.type | Artigo | |
fei.scopus.citations | 5 | |
fei.scopus.eid | 2-s2.0-85059696758 | |
fei.scopus.subject | Complementary metal-oxide-semiconductor (CMOS) integrated circuit | |
fei.scopus.subject | Computational tools | |
fei.scopus.subject | Evolutionary optimisation | |
fei.scopus.subject | Knowledge level | |
fei.scopus.subject | Maximum error | |
fei.scopus.subject | Optimisations | |
fei.scopus.subject | Single stage | |
fei.scopus.subject | Single-ended | |
fei.scopus.updated | 2024-05-01 | |
fei.scopus.url | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85059696758&origin=inward |