Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K

Página do item simplificado
dc.contributor.authorPaz B.C.
dc.contributor.authorCasse M.
dc.contributor.authorBarraud S.
dc.contributor.authorReimbold G.
dc.contributor.authorVinet M.
dc.contributor.authorFaynot O.
dc.contributor.authorPavanello M.A.
dc.date.accessioned2019-08-19T23:45:12Z
dc.date.available2019-08-19T23:45:12Z
dc.date.issued2017
dc.description.abstract© 2016 Elsevier LtdThis work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires with fin width as narrow as 9.5 nm up to quasi-planar MOSFETs 10 μm-wide are analyzed. The fin width influence on the analog parameters is studied for n-type and p-MOSFETs with channel lengths of 10 μm and 40 nm, at room temperature. The temperature influence is analyzed on the analog performance down to 100 K for long channel n-MOSFETs by comparing the quasi-planar device to the nanowire with fin width of 14.5 nm. The intrinsic voltage gain, transconductance and output conductance are the most important figures of merit in this work. An explicit correlation between these figures of merit and the mobility behavior with temperature is demonstrated.
dc.description.firstpage60
dc.description.lastpage66
dc.description.volume128
dc.identifier.citationPAZ, Bruna Cardoso; CASSÉ, MIKAËL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; Pavanello, Marcelo Antonio. Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K. Solid-State Electronics, v. 128, p. 60-66, 2017.
dc.identifier.doi10.1016/j.sse.2016.10.023
dc.identifier.issn0038-1101
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1126
dc.relation.ispartofSolid-State Electronics
dc.rightsAcesso Restrito
dc.subject.otherlanguageAnalog performance
dc.subject.otherlanguageFin width influence
dc.subject.otherlanguageMobility
dc.subject.otherlanguageNanowires
dc.subject.otherlanguageTemperature influence
dc.titleStudy of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K
dc.typeArtigo
fei.scopus.citations11
fei.scopus.eid2-s2.0-85007038282
fei.scopus.subjectAnalog parameters
fei.scopus.subjectAnalog performance
fei.scopus.subjectFigures of merits
fei.scopus.subjectFin widths
fei.scopus.subjectIntrinsic voltage gains
fei.scopus.subjectMobility behavior
fei.scopus.subjectOutput conductance
fei.scopus.subjectTemperature influence
fei.scopus.updated2024-03-04
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85007038282&origin=inward
Arquivos
Coleções
Artigos