Improving MOSFETs' TID Tolerance Through Diamond Layout Style

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dc.contributor.authorSeixas L.E.
dc.contributor.authorGoncalez O.L.
dc.contributor.authorSouza R.
dc.contributor.authorFinco S.
dc.contributor.authorVaz R.G.
dc.contributor.authorDa Silva G.A.
dc.contributor.authorGimenez S.P.
dc.date.accessioned2019-08-19T23:45:29Z
dc.date.available2019-08-19T23:45:29Z
dc.date.issued2017
dc.description.abstract© 2001-2011 IEEE.This letter describes an experimental comparative study of the total ionizing dose (TID) effects due to Co-60 gamma irradiation between hexagonal (Diamond) and conventional rectangular gates metal-oxide semiconductor field-effect transistors (MOSFETs), regarding the same bias conditions during irradiation. The transistors were manufactured by using the 350 nm commercial bulk complementary metal-oxide semiconductor (CMOS) integrated-circuits (ICs) technology. The innovative hexagonal gate layout proposal can reduce the parameter deviations of TID effects in MOSFETs in, approximately, 30%, 400%, and 100% in terms of the threshold voltage, leakage drain current, and subthreshold slope, respectively, regarding the standard MOSFET counterparts. Therefore, the Diamond MOSFET can be considered as a low-cost alternative device to be used in space CMOS ICs applications.
dc.description.firstpage593
dc.description.issuenumber3
dc.description.lastpage595
dc.description.volume17
dc.identifier.citationLuis Eduardo Seixas; GONCALVEZ, O. L.; SOUZA, R.; FINCO, SAULO; G., V. R.; Gabriel Augusto da Silva; GIMENEZ, S. P.. Improving MOSFETs TID Tolerance through Diamond Layout Style. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, v. 1, n. 1, p. 1-1, 2017.
dc.identifier.doi10.1109/TDMR.2017.2719959
dc.identifier.issn1558-2574
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1312
dc.relation.ispartofIEEE Transactions on Device and Materials Reliability
dc.rightsAcesso Restrito
dc.subject.otherlanguageDiamond MOSFET layout style
dc.subject.otherlanguageradiation hardened by design (RHBD)
dc.subject.otherlanguageTID effects
dc.titleImproving MOSFETs' TID Tolerance Through Diamond Layout Style
dc.typeArtigo
fei.scopus.citations12
fei.scopus.eid2-s2.0-85023761528
fei.scopus.subjectComparative studies
fei.scopus.subjectComplementary metal-oxide-semiconductor (CMOS) integrated circuit
fei.scopus.subjectMOS-FET
fei.scopus.subjectParameter deviations
fei.scopus.subjectRadiation hardened by design
fei.scopus.subjectSubthreshold slope
fei.scopus.subjectTID effects
fei.scopus.subjectTotal ionizing dose effects
fei.scopus.updated2024-09-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85023761528&origin=inward
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