Back bias impact on effective mobility of p-type nanowire SOI MOSFETs
dc.contributor.author | PAZ, B .C. | |
dc.contributor.author | CASSE, M. | |
dc.contributor.author | BARRAUD, S. | |
dc.contributor.author | REIMBOLD, G. | |
dc.contributor.author | VINET, M. | |
dc.contributor.author | FAYNOT, O. | |
dc.contributor.author | Marcelo Antonio Pavanello | |
dc.contributor.authorOrcid | https://orcid.org/0000-0003-1361-3650 | |
dc.date.accessioned | 2022-01-12T21:57:06Z | |
dc.date.available | 2022-01-12T21:57:06Z | |
dc.date.issued | 2018-08-27 | |
dc.description.abstract | In this work we investigated the impact of back bias on the effective mobility of p-type Ω-gate nanowire SOI MOSFETs. Evaluation is performed through both measurements and 3D numerical simulations. Electrostatic potential, electric field and holes density are studied through simulations to explain transconductance degradation with back bias increase. Holes mobility linear dependence on back bias is found to be related to the inversion channel density and its position along the silicon thickness. Besides, this work also sheds light on the dependence of the drain current in vertically stacked NW with back bias, as its behavior is determined by the bottom Ω-gate level. | |
dc.identifier.citation | PAZ, B .C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O. PAVANELLO, M. A. Back bias impact on effective mobility of p-type nanowire SOI MOSFETs. 33rd Symposium on Microelectronics Technology and Devices, SBMicro 2018. | |
dc.identifier.doi | 10.1109/SBMicro.2018.8511505 | |
dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/3770 | |
dc.relation.ispartof | 33rd Symposium on Microelectronics Technology and Devices, SBMicro 2018 | |
dc.rights | Acesso Restrito | |
dc.subject.otherlanguage | Back bias | |
dc.subject.otherlanguage | Mobility | |
dc.subject.otherlanguage | Nanowire | |
dc.subject.otherlanguage | SOI | |
dc.subject.otherlanguage | Tridimensional numerical simulations | |
dc.title | Back bias impact on effective mobility of p-type nanowire SOI MOSFETs | |
dc.type | Artigo de evento | |
fei.scopus.citations | 3 | |
fei.scopus.eid | 2-s2.0-85057400450 | |
fei.scopus.subject | 3-D numerical simulation | |
fei.scopus.subject | Back bias | |
fei.scopus.subject | Effective mobilities | |
fei.scopus.subject | Electrostatic potentials | |
fei.scopus.subject | Gate levels | |
fei.scopus.subject | Inversion channels | |
fei.scopus.subject | Linear dependence | |
fei.scopus.subject | Silicon thickness | |
fei.scopus.updated | 2025-02-01 | |
fei.scopus.url | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85057400450&origin=inward |