Analog performance of strained SOI nanowires down to 10K

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dc.contributor.authorPAZ, B. C.
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorCASSE, M.
dc.contributor.authorBARRAUD, S.
dc.contributor.authorREIMBOLD, G.
dc.contributor.authorVINET, M.
dc.contributor.authorFAYNOT, O.
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.date.accessioned2022-01-12T21:58:49Z
dc.date.available2022-01-12T21:58:49Z
dc.date.issued2016-09-15
dc.description.abstractThis work presents the analog performance of strained SOI nanowires for the first time. Triple gate MOSFETs made in strained and unstrained SOI material with variable fin widths from quasi-planar transistors to nanowires with aggressively scaled fin width are compared using experimental results in the temperature range of 300K down to 10K. Intrinsic voltage gain, transconductance and output conductance are the main figures of merit in this work. Transport characteristics are investigated showing that mobility behavior is the major responsible for the analog parameters dependence on temperature.
dc.description.firstpage222
dc.description.lastpage225
dc.description.volume2016-October
dc.identifier.citationPAZ, B. C.; PAVANELLO, M. A.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O. Analog performance of strained SOI nanowires down to 10K. European Solid-State Device Research Conference, p. 222-225, Sept. 2016.
dc.identifier.doi10.1109/ESSDERC.2016.7599626
dc.identifier.issn1930-8876
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3888
dc.relation.ispartofEuropean Solid-State Device Research Conference
dc.rightsAcesso Restrito
dc.subject.otherlanguageAnalog performance
dc.subject.otherlanguageLow temperature
dc.subject.otherlanguageMobility dependence
dc.subject.otherlanguageNanowires
dc.subject.otherlanguageStrained SOI
dc.titleAnalog performance of strained SOI nanowires down to 10K
dc.typeArtigo de evento
fei.scopus.citations3
fei.scopus.eid2-s2.0-84994410850
fei.scopus.subjectAnalog performance
fei.scopus.subjectIntrinsic voltage gains
fei.scopus.subjectLow temperatures
fei.scopus.subjectOutput conductance
fei.scopus.subjectPlanar transistors
fei.scopus.subjectStrained-SOI
fei.scopus.subjectTransport characteristics
fei.scopus.subjectTriple-gate MOSFETs
fei.scopus.updated2024-08-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84994410850&origin=inward
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