Performance and transport analysis of vertically stacked p-FET SOI nanowires

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dc.contributor.authorPAZ, B. C.
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorCASSE, M.
dc.contributor.authorBARRAUD, S.
dc.contributor.authorREIMBOLD, G.
dc.contributor.authorVINET, M.
dc.contributor.authorFAYNOT, O.
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.date.accessioned2022-01-12T21:58:06Z
dc.date.available2022-01-12T21:58:06Z
dc.date.issued2017-06-29
dc.description.abstractThis work presents the performance and transport characteristics of vertically stacked p-MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. Electrical characterization is performed for NWs with [110] and [100] channel orientations, as a function of both fin width (WFIN) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15nm gate length. Improved effective mobility is obtained for [110]-oriented NWs due to higher sidewall mobility contribution.
dc.description.firstpage79
dc.description.lastpage82
dc.identifier.citationPAZ, B. C.; PAVANELLO, M. A.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O. Performance and transport analysis of vertically stacked p-FET SOI nanowires. Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings, p. 79-82, jun. 2017.
dc.identifier.doi10.1109/ULIS.2017.7962606
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3839
dc.relation.ispartofJoint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings
dc.rightsAcesso Restrito
dc.subject.otherlanguagechannel orientation
dc.subject.otherlanguageelectrical characterization
dc.subject.otherlanguageperformance
dc.subject.otherlanguageSOI MOSFET
dc.subject.otherlanguagetransport
dc.subject.otherlanguagevertically stacked nanowire
dc.titlePerformance and transport analysis of vertically stacked p-FET SOI nanowires
dc.typeArtigo de evento
fei.scopus.citations4
fei.scopus.eid2-s2.0-85026737766
fei.scopus.subjectChannel orientations
fei.scopus.subjectElectrical characterization
fei.scopus.subjectperformance
fei.scopus.subjectSOI-MOSFETs
fei.scopus.subjecttransport
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85026737766&origin=inward
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