Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance

Página do item simplificado
dc.contributor.authorRodrido Doria
dc.contributor.authorTREVISOLI, R. D.
dc.contributor.authorMichelly De Souza
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-6472-4807
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-4448-4337
dc.date.accessioned2022-01-12T22:02:43Z
dc.date.available2022-01-12T22:02:43Z
dc.date.issued2012-09-02
dc.description.abstractThe self-cascode (SC) configuration consists in a series association of two transistors with tied gates usually applied to improve the analog performance of MOS devices. This paper compares the analog parameters of single Junctionless transistors with the ones presented by self-cascode associations composed by two Junctionless devices with identical or different fin widths (symmetric and asymmetric, respectively). The transconductance to the drain current ratio, the Early voltage (VEA) and the intrinsic voltage gain (AV) have been evaluated for both single devices and SC structures. It has been shown that the SC configurations, specially the asymmetric ones, present a strong reduction of the drain conductance (gD) with respect to single devices, resulting in an increase of VEA and AV, which can be higher than 30 dB depending on the bias conditions. © The Electrochemical Society.
dc.description.firstpage215
dc.description.issuenumber1
dc.description.lastpage222
dc.identifier.citationDORIA, R.; TREVISOLI, R. D.; DE SOUZA, M.; PAVANELLO, M. A. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance. ECS Transactions, v, 49, n. 1, p. 215-222, 2012.
dc.identifier.doi10.1149/04901.0215ecst
dc.identifier.issn1938-6737
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4154
dc.relation.ispartofECS Transactions
dc.rightsAcesso Restrito
dc.titleApplication of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance
dc.typeArtigo de evento
fei.scopus.citations8
fei.scopus.eid2-s2.0-84875859861
fei.scopus.subjectAnalog parameters
fei.scopus.subjectAnalog performance
fei.scopus.subjectBias conditions
fei.scopus.subjectDrain conductance
fei.scopus.subjectIntrinsic voltage gains
fei.scopus.subjectJunctionless devices
fei.scopus.subjectJunctionless transistors
fei.scopus.subjectNanowire transistors
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84875859861&origin=inward
Arquivos
Coleções
Artigos