Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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Resultados da Pesquisa
- Impact of using Octogonal Layout Style in Planar Power MOSFETs(2022-08-22) DA SILVA, G. A.; Salvador Gimenez© 2022 IEEE.Previous studies have already shown that the use of alternative gate shapes for planar and tridimensional MOSFETs are capable of boosting their analog and digital electrical performances and their ionizing radiations robustness. In this scenario, this work has the objective to study the impact of the use of octagonal layout style (OCTO), as the basic cell, to the implementing of the Planar Power MOSFET (PPM). The main results of this paper show that the PPM layouted with OCTO layout styles, as the basic cells, are able to improve the drain saturation current (IDS-sat) about 668%%, in relation to that implemented with conventional rectangular layout style, considering that they present the same gate area and bias conditions. Therefore, this type of layout approach can be considered an alternative layout to improve the electrical performance of PPMs.
- Boosting the performance of the planar power MOSFET By using Diamond layout style(2014-09-05) DA SILVA, G. A.; Salvador Gimenez© 2014 IEEE.This manuscript introduces and experimentally investigates, for the first time, the Planar Power MOSFETs implemented with Diamond (hexagonal gate geometry) Metal-Oxide-Semiconductor Field Effect Transistor with different a angles, as a basic cell, in comparison to the homologous Multifinger PPM, regarding the same gate die area and bias conditions. Using the DPPM as output current driver (switch) in digital integrated circuits applications, we can remarkably boost the PPM electrical performance in relation to the MPPM, considering the same gate area (AG) and bias conditions (BC).
- Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs(2021-01-05) BANIN JUNIO, J. R. BANIN JUNIO, J. R.; MORETO R. A. L.; DA SILVA, G. A.; THOMAZ, C. E.; GIMENEZ, S. Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs. Analog Integrated Circuits and Signal Processing, v. 106, n. 1, p. 293-306, Jan. 2021.; MORETO R. A. L.; DA SILVA, G. A.; THOMAZ, C. E.; Salvador Gimenez© 2020, Springer Science+Business Media, LLC, part of Springer Nature.This paper describes a pioneering methodology to design, optimize, and reduce the total gate area of robust Operational Transconductance Amplifiers (OTAs). The Single-Ended Single-Stage (SESS) OTA has been chosen to validate the proposed technique by using the 180 nm planar Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technology. The Electronic Design Automationtool, named iMTGSPICE, was used to design and optimize the SESS OTA. There are several heuristics optimization techniques of Artificial Intelligence to optimize analog and radio-frequency CMOS ICs, but we have selected to use the Genetic Algorithm because it presents the best optimization performance among the other algorithms previously studied. This paper also describes a procedure of converting the Conventional planar MOSFETs (rectangular gate shape) into the Diamond MOSFETs (hexagonal gate shape) with the same electrical performance. Furthermore, it is proposed a procedure to simulate the Diamond MOSFETs (DMs) in the Simulation Program with Integrated Circuit Emphasis (SPICE) because there is still no SPICE model to perform the DM. Additionally, this work proposes a methodology to layout OTAs with Diamond MOSFETs, regarding different values of aspect ratios. The main result of this work reveals a total gate area reduction of approximately 30% of a robust OTA implemented with Diamond MOSFETs, with an alpha angle (α) equal to 45°, with respect to the one observed in the robust OTA implemented with standard MOSFETs, maintaining practically the same electrical performance and robustness.