Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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Resultados da Pesquisa
- Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS(2006) Gimenez S.P.; Pavanello M.A.; Martino J.A.; Flandre D.This paper studies the performance of operational transconductance amplifiers (OTAs) fabricated with Graded-Channel (GC) SOI nMOSFETs and designed to provide high open-loop voltage gain or high gain-bandwidth characteristics. Different design targets were taken in account such as similar power dissipation, transconductance over drain current ratio and die area. Comparisons with OTAs made with conventional SOI nMOSFETs, are performed showing that the GC OTAs presents larger open-loop voltage gain without degrading the phase margin, unit gain frequency and slew rate simultaneously with a significant required die area reduction depending on LLD/L ratio used. Circuit simulations and experimental results are used to qualify the analysis. © 2005 Elsevier Ltd. All rights reserved.
- Evaluation of graded-channel SOI MOSFET operation at high temperatures(2006) Galeti M.; Pavanello M.A.; Martino J.A.This paper presents a comparative analysis between graded-channel (GC) and conventional fully depleted SOI MOSFETs devices operating at high temperatures (up to 300 °C). The electrical characteristics such as threshold voltage and subthreshold slope were obtained experimentally and by two-dimensional numerical simulations. The results indicated that GC transistors present nearly the same behavior as the conventional SOI MOSFET devices with similar channel length. Experimental analysis of the gm/IDS ratio and Early voltage demonstrated that in GC devices the low-frequency open-loop gain is significantly improved in comparison to conventional SOI devices at room and at high-temperature due to the Early voltage increase. The multiplication factor and parasitic bipolar transistor gain obtained by two-dimensional numerical simulations allowed the analysis of the breakdown voltage, which was demonstrated to be improved in the GC as compared to conventional SOI transistors in thin silicon layer devices in the whole temperature range under analysis. © 2005 Elsevier Ltd. All rights reserved.
- Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications(2006) Pavanello M.A.; Der Agopian P.G.; Martino J.A.; Flandre D.We present in this work an analysis of the low temperature operation of Graded-Channel fully depleted Silicon-On-Insulator (SOI) nMOSFETs for analog applications, in the range of 100-300 K. This analysis is supported by a comparison between the results obtained by two-dimensional numerical simulations and measurements in the whole temperature range under study. The Graded-Channel transistor presents higher Early voltage if compared to the conventional fully depleted SOI nMOSFET, without degrading the transconductance over drain current, at all studied temperatures, leading to a gain larger than 20 dB compared to the conventional SOI. The resulting higher gain lies in the improvement of the electric field distribution and impact ionization rate by the graded-channel structure. © 2005 Elsevier Ltd. All reserved.