Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
Navegar
1 resultados
Resultados da Pesquisa
- Modeling of silicon stacked nanowire and nanosheet transistors at high temperatures(2022-07-04) CERDEIRA, A.; ESTRADA, M.; DA SILVA, G. M.; RODRIGUES, J. C.; Marcelo Antonio Pavanello© 2022 IEEE.In this work, we demonstrate that the Symmetric Doped Double-Gate Model (SDDGM), previously validated for modeling FinFETs, stacked nanowire, and nanosheet transistors at room temperature, can be extended for modeling stacked nanowire and nanosheet transistors at high temperatures. The modeled results are validated by comparison with experimental data.