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URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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Artigo 0 Citação(ões) na Scopus A simple electron mobility model considering the silicon-dielectric interface orientation for circular surrounding-gate transistor(2012-01-05) PERIN, A. L.; PEREIRA, A. S. N.; AGOPIAN, P. G. D.; Joao Antonio Martino; Giacomini R.AIn this work, a simple model that accounts for the variation of electron mobility as a function of the silicondielectric interface crystallographic orientation is presented. Simulations were conducted in order to compute the effective mobility of planar devices and its results were compared to experimental data for several interface orientations. The error between experimental data and the proposed model remained bellow 4%. The model has been applied to nMOS circular surrounding gate (thin-pillar transistor - CYNTHIA) and allowed the observationof current density variations as a function of the interface orientation around the silicon pillar.- Effect of substrate bias and temperature variation in the capacitive coupling of soi utbb mosfets(2021-08-23) DA SILVA, E. M.; TREVISOLI, R.; Rodrido Doria© 2021, Brazilian Microelectronics Society. All rights reserved.In this work, the electrical features related to the capacitive coupling and temperature influence of the Ultra-Thin Body and Buried Oxide SOI MOSFET (UTBB) transistors are explored through numerical simulations calibrated to experimental data. The impact of the substrate bias is observed for a set of values ranging from-3 V to 2 V for a temperature range between 100 K and 400 K. Also, structures with n-and ptype ground planes (GP-P and GP-N) and without GP have been evaluated. This approach analyzes the capacitive coupling through the body factor and shows that the negative biasing for all GP types significantly improves the structure coupling and that the device with P-type ground plane has the lowest value of body factor for all the evaluated conditions. The dependence of the body factor on the temperature has shown to be negligible for longer devices. However, for devices shorter than 50 nm, the position of the maximum electrons concentration inside the silicon layer may affect the capacitive coupling.