Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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8 resultados
Resultados da Pesquisa
- Electrical behavior of the Diamond layout style for MOSFETs in X-rays ionizing radiation environments(2015) Gimenez S.P.; Alati D.M.© 2015 Elsevier B.V. All rights reserved.This paper aims to describe some innovative layout styles, which are capable to boost the electrical performance and, in the same time, the Total Ionizing Dose (TID) tolerance of Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), without burdening the current planar Complementary MOS (CMOS) Integrated Circuits (ICs) manufacturing processes. To illustrate the potential use of these new alternative devices in analog and digital CMOS ICs applications, this work focuses on the Diamond layout style for MOSFET that presents hexagonal gate geometry. The new effects associated to this innovative transistor structure and its modeling are presented and discussed in detail. Some experimental results are illustrated to evidence its use mainly in space and medical CMOS ICs applications.
- Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors(2019) Trevisoli R.; Doria R.T.; Barraud S.; Pavanello M.A.© 2019 Elsevier B.V.The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire Transistors. The proposed model is based on a drain current model, which includes short channel effects influence. The surface potential and the occupied trap density equations are solved self consistently to obtain the traps influence in the static drain current, which is used to determine the trap-related noise. In this work, the low frequency noise of traps in discrete levels is analyzed. The model has been validated with 3D simulations considering different devices characteristics, biases and trap levels. Experimental results have also been used to demonstrate the model suitability.
- Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization(2017) Doria R.T.; Trevisoli R.; de Souza M.; Barraud S.; Vinet M.; Faynot O.; Pavanello M.A.© 2017 Elsevier B.V.This work presents, for the first time, an experimental analysis of the low-frequency noise and the effective trap density dependence of junctionless nanowire transistors (JNTs) on the substrate bias. The study has been performed for devices with different channel lengths and doping concentrations biased close to the threshold and deep in linear regime. It has been shown that the surface potential of JNTs is strongly influenced by the substrate bias even above threshold. Thus, the drain current noise spectral density and the effective trap density can be improved or degraded depending on the bias applied to the substrate of the devices. Additionally, it is shown that, the variation on the substrate bias enables the evaluation of traps with different activation energy ranges, which is more evident in heavier doped devices due to the higher threshold voltage sensitivity to the substrate bias.
- Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior(2007) de Souza M.; Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C.This work presents the impact of low temperature operation on the characteristics of uniaxially strained fully-depleted SOI nMOSFETs. Devices with channel lengths down to 160 nm were explored in the range 100-380 K. The maximum transconductance in linear region was used to evaluate the mobility enhancement. Besides the increased mobility provided by the strain in comparison to its unstrained SOI counterpart, higher mobility degradation for high values of applied gate voltage was observed. The subthreshold slope and the Drain Induced Barrier Lowering (DIBL) of short-channel devices have been also analyzed, showing that strained devices are more susceptible to the occurrence of short-channel effects. © 2007 Elsevier B.V. All rights reserved.
- Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors(2015) Trevisoli R.; Doria R.T.; De Souza M.; Pavanello M.A.© 2015 Elsevier B.V. All rights reserved.Abstract This work proposes a method for extracting the energetic distribution of the interface trap density at the gate dielectric in Junctionless silicon Nanowire Transistors. The proposed method uses the subthreshold slope extraction combined with the substrate bias in order to induce a variation in the channel potential, such that the interface trap density can be extracted for a significant energy range. Three-dimensional TCAD numerical simulations have been performed to analyze the accuracy of the proposed method considering different concentrations and trap density profiles (uniform and exponential). The influence of the device width variation on the trap energy determination has been analyzed, showing that only for positive substrate biases the energy might be affected. The method precision was also analyzed, showing that the trap density extraction is only effectively affected for low Nit values, which do not influence significantly the device performance. Finally, the method has been applied to experimental transistors with high-κ and silicon dioxide gate dielectrics showing consistent results.
- In-depth low frequency noise evaluation of substrate rotation and strain engineering in N-type triple gate SOI Finfets(2015) Doria R.T.; De Souza M.A.S.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A.© 2015 Elsevier B.V. All rights reserved.This work presents an experimental analysis of the low-frequency noise and the effective trap density of conventional, strained, rotated and strained-rotated SOI n-type FinFETs, respectively, for several fin widths biased at different gate voltages. Additionally, the profile of the effective trap density is presented along the depth of the gate dielectric of the devices. It is shown that strained devices present higher noise than conventional ones, independent on the fin width, which can be explained by poorer interface quality observed in strained devices. On the other hand, the low frequency noise of narrow rotated devices, where the main conduction path changes from top to sidewalls, has shown to reduce as the interface integrity is improved by substrate rotation. All the evaluated devices presented 1/f noise as the dominant noise component up to 1 kHz.
- Trap density characterization through low-frequency noise in junctionless transistors(2013) Doria R.T.; Trevisoli R.D.; De Souza M.; Pavanello M.A.This work evaluates, for the first time, the trap density of Junctionless Nanowire Transistors (JNTs) of two technologies produced with different gate dielectrics through the low-frequency noise (LFN) characterization. Along the work, the LFN resultant from both devices was compared in linear and saturation regimes for different gate biases, showing that these devices can exhibit either 1/f or Lorentzian as the dominant noise source depending on the technology and gate bias. Such analysis showed that devices with SiO2 gate dielectric have presented only one corner frequency over the whole frequency range whereas two corner frequencies with different time constants could be observed in devices with HfSiON gate dielectric. The trap density of both devices showed to be similar to the values reported for inversion mode devices in different recent papers, in the order of 1016 cm-3 eV-1 and 1019 cm-3 eV-1, for SiO2 and HfSiON gate dielectrics, respectively.© 2013 Elsevier B.V.All rights reserved.
- 3D simulation of triple-gate MOSFETs with different mobility regions(2011-07-05) CONDE, J.; CERDEIRA, A.; Marcelo Antonio Pavanello; KILCHYTSKA, V.; FLANDRE, D.In this paper we present a new approach for analyzing 3D structure triple-gate MOSFETs using three different regions, one at the top and two in the sidewalls of the fin, which allows for considering different carrier mobilities in each region due to crystalline orientation and technological processing. A procedure for the extraction of the mobility parameters in each region is developed. Robustness of the proposed structure is validated by experimental data obtained on FinFETs. A very good agreement is obtained between experimental and simulated characteristics. © 2011 Elsevier B.V. All rights reserved.