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Analysis of silicon thickness reduction on analog parameters of GC GAA SOI transistors operating up to 300°C
(2006-09-01) SANTOS, C. D. G. DOS; Marcelo Antonio Pavanello; Joao Antonio Martino
This paper analyzes the impact of silicon film thickness reduction in some analog parameters of Gate-All-Around (GAA) transistors using the graded-channel (GC) architecture. The study was done at high temperatures (up to 300°C) through two-dimensional simulations. As the silicon film is reduced an improvement on the Early voltage was observed. However, for GC GAA devices this improvement is more pronounced at room temperature than at high temperatures. The output swing voltage (Vos) was also studied and it decreases while reducing the silicon thickness. Regarding the GC GAA the Vos is larger than conventional GAA in 50 nm thick transistors. © 2006 The Electrochemical Society.
Influence of non-vertical sidewall on finfet threshold voltage
(2006-08-28) Renato Giacomini; Joao Antonio Martino
The FinFET structure is one of the most promising architecture approaches to double-gate devices. Due to limitations of process uniformity, most fabricated FinFETs have width variation along the vertical direction, resulting in non-vertical sidewalls. The impact of non-vertical sidewalls on the threshold voltage of FinFETs is studied in this work through three-dimensional simulation. The main purpose of this study is to verify the applicability of some analytical models developed to double-gate devices with parallel gates to FinFETs with inclined sidewalls. The behavior of the threshold voltage for different doping levels and silicon film width is discussed. The use of the existing models taking an average width of the silicon film as the device width is proposed and shows to be a good approximation. © 2006 The Electrochemical Society.

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