Repositório do Conhecimento Institucional do Centro Universitário FEI
 

Engenharia Elétrica

URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21

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2017 - 201922020 - 20221

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Autor: search.filters.author.ALVES, C. R.Assunto: search.filters.subject.Graded channels

Resultados da Pesquisa

Agora exibindo 1 - 3 de 3
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    Artigo de evento 2 Citação(ões) na Scopus
    Comparative Analysis of Transcapacitances in Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs
    (2022-07-04) ALVES, C. R.; D'OLIVEIRA, L. M.; Michelly De Souza
    © 2022 IEEE.This work presents a comparative study of the transcapacitances of asymmetric self-cascode (A-SC) and graded-channel (GC) silicon-on-insulator (SOI) nMOSFETs, by means of two-dimensional numerical simulations. Simulated results show that the gate-to-drain capacitance is smaller for the ASC SOI device if compared to the GC SOI device, despite of the applied VDS.
  • N/D
    Artigo de evento 1 Citação(ões) na Scopus
    Experimental evaluation of mismatching on the analog characteristics of GC SOI MOSFETs
    (2017-07-28) ALVES, C. R.; Marcelo Antonio Pavanello; Michelly De Souza; FLANDRE, D.
    This paper presents an experimental study of mismatching on the analog characteristics of fully-depleted graded-channel SOI MOSFET in comparison to uniformly doped transistors. The study is carried out using dedicated structures to account for the mismatch that have been fabricated at the same chip and with the same technology. Important basic parameters such as threshold voltage and subthreshold slope were analyzed as well as analog parameters, namely transconductance, output conductance, Early voltage and intrinsic voltage gain.
  • N/D
    Artigo de evento 2 Citação(ões) na Scopus
    Numerical simulation and analysis of transistor channel length and doping mismatching in GC SOI nMOSFETs analog figures of merit
    (2018-08-31) ALVES, C. R.; Michelly De Souza; FLANDRE, D.
    © 2018 IEEE.This paper presents a two-dimensional numerical simulation study of mismatching on the analog characteristics of fully-depleted graded-channel (GC) SOI MOSFET. The study aims at identifying the mismatching sources that affect the analog performance of GC SOI transistors. The simulations were performed imposing length and doping concentration variations and analyzing its impact on important electrical parameters such as threshold voltage and subthreshold slope, as well as analog parameters, namely transconductance, output conductance, Early voltage and intrinsic voltage gain.