Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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2 resultados
Resultados da Pesquisa
- Analysis of harmonic distortion of asymmetric self-cascode association of SOI nMOSFETs operating in saturation(2014-01-20) D'OLIVEIRA, L. M.; Rodrigo Doria; Marcelo Antonio Pavanello; Michelly De Souza; FLANDRE, D.This paper presents an experimental analysis of the harmonic distortion of asymmetric self-cascode (A-SC) association of SOI transistors. This goal is achieved by comparing the A-SC to the symmetric self-cascode (S-SC) configuration with different channel lengths. The non-linearity data have been obtained by applying the Integral Function Method to experimental measurements, for the evaluation of the total and third-order harmonic distortion. The results show that the asymmetric self-cascode provides lower total harmonic distortion than S-SC for all studied channel length associations. If a target distortion level is fixed, the A-SC enables an increase of input signal amplitude. On the other hand, smaller input signal amplitude and distortion are verified in the A-SC when fixing the output amplitude.
- Subthreshold Operation of Self-Cascode Structure Using UTBB FD SOI Planar MOSFETs(2019-10-17) D'OLIVEIRA, L. M.; KILCHYTSKA, V.; PLANES, N.; FLANDRE, D.; Michelly De Souza© 2019 IEEE.This paper presents an experimental analysis of the analog characteristics of self-cascode structures composed by 28 nm technological node ultra-thin body and BOX fully-depleted silicon-on-insulator planar MOSFETs, focusing on the subthreshold operation regime. Apart from the increased gain promoted by the reduction of front gate voltage, there is further improvement when the back-gate bias is used to reduce the threshold voltage of transistor close to the drain of the composite device, making this structure a promising option for low-power low-voltage (LPLV) analog applications.