Subthreshold Operation of Self-Cascode Structure Using UTBB FD SOI Planar MOSFETs
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2019-10-17
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D'OLIVEIRA, L. M.
KILCHYTSKA, V.
PLANES, N.
FLANDRE, D.
Michelly De Souza
KILCHYTSKA, V.
PLANES, N.
FLANDRE, D.
Michelly De Souza
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2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
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D'OLIVEIRA, L. M.; KILCHYTSKA, V.; PLANES, N.; FLANDRE, D.; DE SOUZA, M. Subthreshold Operation of Self-Cascode Structure Using UTBB FD SOI Planar MOSFETs. 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019, Oct. 2019.
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© 2019 IEEE.This paper presents an experimental analysis of the analog characteristics of self-cascode structures composed by 28 nm technological node ultra-thin body and BOX fully-depleted silicon-on-insulator planar MOSFETs, focusing on the subthreshold operation regime. Apart from the increased gain promoted by the reduction of front gate voltage, there is further improvement when the back-gate bias is used to reduce the threshold voltage of transistor close to the drain of the composite device, making this structure a promising option for low-power low-voltage (LPLV) analog applications.