Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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8 resultados
Resultados da Pesquisa
- Junctionless nanowire transistors parameters extraction based on drain current measurements(2019) Trevisoli R.; Doria R.T.; de Souza M.; Barraud S.; Pavanello M.A.© 2019 Elsevier LtdThe aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As junctionless devices present a different conduction mechanism than inversion-mode transistors, the methods developed for the latter devices either are not compatible or cannot be directly applied to JNTs before a deep analysis on their applicability. The current work analyzes the extraction of the series resistance, including a discussion about the influence of the first and second order mobility degradation factors, flatband voltage and low field mobility in junctionless transistors based only on static drain current curves. An analysis of the method accuracy considering the influence of the channel length, nanowire width and height, gate oxide thickness and doping concentration is also presented for devices with different characteristics through three-dimensional numerical simulations. The inclusion of the second order effects in a drain current model is also shown, considering the extracted values. The method applicability is also successfully demonstrated in experimental devices.
- Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range(2019) Pavanello M.A.; Cerdeira A.; Doria R.T.; Ribeiro T.A.; Avila-Herrera F.; Estrada M.© 2019 Elsevier LtdThis paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range from room temperature up to 500 K. The model validation is performed by comparison against tridimensional numerical simulation and experimental data showing very good agreement, with continuous description of drain current and its derivatives in all regions of operation and temperatures.
- Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45 rotated substrates(2013) Doria R.T.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A.This paper studies the impact of the 45 substrate rotation on the low-frequency noise (LFN) of triple gate nFinFETs. The overall LFN has been extracted for both standard and 45 substrate rotated devices of several fin widths at different drain and gate voltage biases focusing on their operation in saturation regime. A general view of the mechanisms which govern the low-frequency noise in MOS devices is provided and a brief discussion on the physical origins of the LFN in the evaluated devices is carried out. It has been noted that the LFN in non-rotated (0 rotated) and 45 rotated devices operating in the linear regime shows 1/f behavior independent on the gate bias, whereas in the saturation regime both 1/f and Lorentzian (1/f2) noises are observed. The former one prevails at lower frequencies and the 1/f2 noise at higher ones. In this case, the corner frequency shows an exponential dependence on the gate bias. © 2013 Elsevier Ltd. All rights reserved.
- On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration(2016) De Souza M.; Flandre D.; Doria R.T.; Trevisoli R.; Pavanello M.A.© 2015 Elsevier Ltd. All rights reserved.This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two transistors connected in series with gates shortened, acting as a single device. The doping concentration of the two transistors in the structure is different, leading to higher threshold voltage of the transistor at the source side of the composite structure than that of the transistor at the drain side. By reducing the doping concentration level at the channel of the transistor at drain side of the composite structure, forcing it to work in saturation, part of the applied drain bias is absorbed and does not reach the transistor close to the source, which is the main responsible for the overall device characteristics. As a result, larger drain current level and transconductance are obtained in comparison to symmetric self-cascode (where both transistors present same doping level) apart from promoting output conductance reduction. The transconductance, output conductance, Early voltage, and intrinsic voltage gain are used as figures of merit to demonstrate and validate the advantages of the proposed structure. The influence of channel length and doping concentration are also evaluated. The A-SC configuration is fully compatible with any standard FD SOI MOSFET technology with multiple threshold voltages. A simulation analysis demonstrates the feasibility of the proposed asymmetric structure in a UTBB FD SOI technology.
- Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors(2014) Doria R.T.; Trevisoli R.; De Souza M.; Pavanello M.A.This work presents an evaluation of the Low-Frequency Noise (LFN) exhibited by short-channel Junctionless Nanowire Transistors (JNTs). Unlike in previous works in which only the noise of n-type transistors was evaluated, this paper exhibits an analysis of both the LFN and the effective trap density of n- and p-type JNTs. The low-frequency noise is analyzed in terms of the channel length as well as doping concentration and has shown to be nearly independent on the former parameter when the device is biased above threshold and to decrease with the raise of the latter. Also, carrier number fluctuations dominate the LFN in nMOS JNTs whereas an important mobility fluctuation component is present in the pMOS ones. The effective trap density of JNTs has shown to be in the order of 1019 cm-3 eV-1, presenting its maximum around 1.4 nm away from the silicon/gate dielectric interface independently on the device type or doping concentration. © 2014 Elsevier Ltd. All rights reserved.
- Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors(2013) Cerdeira A.; Estrada M.; Iniguez B.; Trevisoli R.D.; Doria R.T.; De Souza M.; Pavanello M.A.A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors (SDGJLTM) is proposed and validated with simulations for doping concentrations of 5 × 1018 and 1 × 10 19 cm-3, as well as for layer thicknesses of 10, 15 and 20 nm. The model is physically-based, considering both the depletion and accumulation operating conditions. Most model parameters are related to physical magnitudes, and the extraction procedure for each of them is well established. The model provides an accurate description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of the requirement of being symmetrical with respect to Vd = 0 V. © 2013 Elsevier Ltd. All rights reserved.
- A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors(2013) Trevisoli R.D.; Doria R.T.; De Souza M.; Pavanello M.A.This work proposes a physically-based definition for the threshold voltage, VTH, of junctionless nanowire transistors and a methodology to extract it. The VTH is defined as the point of equal magnitude for the drift and diffusion components of the drain current. The methodology for VTH extraction uses the device transconductance over drain current ratio characteristics. An analytical model for the threshold voltage based on the same definition has also been developed. Both VTH extraction method and model have been validated through 3D simulations and have been applied to experimental devices. The proposed method has shown to provide a correct dependence on the temperature, while the double derivative of the drain current method overestimates this variation. © 2013 Elsevier Ltd. All rights reserved.
- Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS(2011) Doria R.T.; Simoen E.; Claeys C.; Martino J.A.; Pavanello M.A.This work investigates the harmonic distortion (HD) in 2-MOS balanced structures composed of triple gate FinFETs. HD has been evaluated through the determination of the third-order harmonic distortion (HD3), since this represents the major non-linearity source in balanced structures. The 2-MOS structures with devices of different channel lengths (L) and fin widths (W fin) have been studied operating in the linear region as tunable resistors. The analysis was performed as a function of the gate voltage, aiming to verify the correlation between operation bias and HD3. The physical origins of the non-linearities have been investigated and are pointed out. Being a resistive circuit, the 2-MOS structure is generally projected for a targeted on-resistance, which has also been evaluated in terms of HD3. The impact of the application of biaxial strain has been studied for FinFETs of different dimensions. It has been noted that HD3 reduces with the increase of the gate bias for all the devices and this reduction is more pronounced both in narrower and in longer devices. Also, the presence of strain slightly diminishes the non-linearity at a similar bias. However, a drawback associated with the use of strain engineering consists in a significant reduction of the on-resistance with respect to unstrained devices. © 2011 Elsevier Ltd. All rights reserved.