Repositório do Conhecimento Institucional do Centro Universitário FEI
 

Engenharia Elétrica

URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21

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2017 - 20182

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Autor: search.filters.author.FAYNOT, O.Periódico: search.filters.ispartof.2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

Resultados da Pesquisa

Agora exibindo 1 - 2 de 2
  • N/D
    Artigo de evento 0 Citação(ões) na Scopus
    Analog performance of self-cascode SOI nanowires nMOSFETs aiming at low-power applications
    (2018) ASSALTI, R.; Michelly De Souza; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.
    © 2017 IEEE.This paper experimentally explores the analog performance of Self-Cascode structures composed by SOI Nanowire nMOSFETs operating near the subthreshold regime. The composite structure uses transistors with distinct channel widths, biased in several back-gate voltages, to promote different threshold voltages.
  • N/D
    Artigo de evento 4 Citação(ões) na Scopus
    New method for individual electrical characterization of stacked SOI nanowire MOSFETs
    (2017-10-18) PAZ, B.C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello
    A new systematic procedure to separate the electrical characteristics of advanced stacked nanowires (NWs) with emphasis on mobility extraction is presented. The proposed method is based on I-V measurements varying the back gate bias (VB) and consists of three basic main steps, accounting for VB influence on transport parameters. Lower mobility was obtained for the top GAA NW in comparison to bottom Q-NW. Temperature dependence of carrier mobility is also studied through the proposed method up to 150°C.