Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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10 resultados
Resultados da Pesquisa
- Substrate bias influence on the operation of junctionless nanowire transistors(2014) Trevisoli R.; Doria R.T.; De Souza M.; Pavanello M.A.The aim of this paper is to analyze the substrate bias influence on the operation of junctionless nanowire transistors based on 3-D simulated and experimental results, accomplished by modeled data. The threshold voltage, the maximum transconductance, the subthreshold slope, the drain-induced barrier lowering (DIBL), and the ION/IOFF ratio are the key parameters under analysis. It has been shown that the negative back bias can reduce the short-channel effects occurrence, improving the ION/ OFF ratio and DIBL. © 1963-2012 IEEE.
- Junctionless nanowire transistors parameters extraction based on drain current measurements(2019) Trevisoli R.; Doria R.T.; de Souza M.; Barraud S.; Pavanello M.A.© 2019 Elsevier LtdThe aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As junctionless devices present a different conduction mechanism than inversion-mode transistors, the methods developed for the latter devices either are not compatible or cannot be directly applied to JNTs before a deep analysis on their applicability. The current work analyzes the extraction of the series resistance, including a discussion about the influence of the first and second order mobility degradation factors, flatband voltage and low field mobility in junctionless transistors based only on static drain current curves. An analysis of the method accuracy considering the influence of the channel length, nanowire width and height, gate oxide thickness and doping concentration is also presented for devices with different characteristics through three-dimensional numerical simulations. The inclusion of the second order effects in a drain current model is also shown, considering the extracted values. The method applicability is also successfully demonstrated in experimental devices.
- Physical insights on the dynamic response of SOI n-and p-type junctionless nanowire transistors(2018) Doria R.T.; Trevisoli R.; de Souza M.; Pavanello M.A.© 2018, Brazilian Microelectronics Society. All rights reserved.— This work evaluates, for the first time, the roles of the intrinsic capacitances and the series resistance on the dynamic response of p-and n-type Junctionless Nanowire Transistors. The dynamic behavior evaluation will be carried out through the analysis of the limitation imposed by such parameters on the maximum oscillation frequency (fmax). In the sequence, it will be shown the impacts of fmax and the carriers’ transit time on the minimum switching time presented by JNTs. It has been observed that Junctionless devices present lower fmax than inversion mode transistors of similar dimensions due to higher resistance and lower transconductance. However, the intrinsic capacitances of such devices are smaller than the inversion mode ones, which compensates part of the degradation on fmax caused by the other parameters. Besides that, it is shown that transit time can be important on the dynamic behavior of long devices, but plays a negligible role in shorter ones.
- Drain current model for short-channel triple gate junctionless nanowire transistors(2016) Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Faynot O.; Avila-Herrera F.; Cerdeira A.; Pavanello M.A.© 2016 Elsevier LtdThis work proposes a numerical charge-based new model to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration of a single expression that physically describes the junctionless charge density in both accumulation and depletion regimes of operation, leading to a continuous model in all operational regions. The triple gate structure is modeled from an evolution of a previous model designed for double gate junctionless nanowire transistors (2G JNT). Improvements concerning the capacitance coupling, the internal potential changing while reducing the fin height in nanowire transistors and higher immunity to short-channel effects (SCE) are considered. The model validation is performed through both tridimensional numerical simulation and experimental measurements for long and short-channel devices. Through simulated results, it is verified the agreement of the modeled curves for junctionless transistors with different values of fin height. Comparison between the proposed model and experimental data is performed for 3G JNT advanced structures with channel length down to 15 nm and fin height of 8 nm. Results for 3G JNTs with different values of doping concentration and channel width are also displayed showing a good agreement as well. Moreover, 3G JNT performance is also analyzed and compared in the studied structures by extracting the threshold voltage (VTH), subthreshold slope (S), DIBL and model parameters.
- Junctionless nanowire transistors operation at temperatures down to 4.2 K(2016) Trevisoli R.; De Souza M.; Doria R.T.; Kilchtyska V.; Flandre D.; Pavanello M.A.© 2016 IOP Publishing Ltd.The aim of this work is to analyze the operation of junctionless nanowire transistors down to the liquid helium temperature. The drain current, the transconductance, the output conductance, the subthreshold slope, the threshold voltage and the interface trap density are the key parameters under analysis, which has been performed through experimental results together with simulated data. Oscillations in the transconductance and output conductance have been observed in the experimental results of junctionless devices for temperatures lower than 77 K. The experimental drain current curves also exhibited a 'drain threshold voltage' for the lower temperatures. The impact of the source/drain contact resistance and discrete trap levels has been analyzed by means of simulations.
- Charge-based compact analytical model for triple-gate junctionless nanowire transistors(2016) Avila-Herrera F.; Paz B.C.; Cerdeira A.; Estrada M.; Pavanello M.A.© 2016 Elsevier Ltd.A new compact analytical model for short channel triple gate junctionless transistors is proposed. Based on a previous model for double-gate transistors which neglected the fin height effects, a new 3-D continuous model has been developed, including the dependence of the fin height and the short channel effects. An expression for threshold voltage is presented. The model defines a one-dimensional semiconductor effective capacitance due to the width and the height of the fin, which in turn redefines the potentials and charges, without altering the general modeling procedure. Threshold voltage roll-off, subthreshold slope, DIBL and channel length modulation, as well as, the mobility degradation and the velocity saturation have been introduced into the model. The validation was done by 3-D numerical simulations for different fin heights and channel lengths, as well as, by experimental measurements in nanowire transistors with doping concentrations of 5 × 1018 and 1 × 1019 cm-3. The developed model is suitable for describing the current-voltage characteristics in all operating regions from double-gate to nanowire transistor with only 8 adjusting parameters.
- Compact model for short-channel symmetric double-gate junctionless transistors(2015) Avila-Herrera F.; Cerdeira A.; Paz B.C.; Estrada M.; Iniguez B.; Pavanello M.A.© 2015 Elsevier Ltd.Abstract In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage roll-off, series resistance, drain saturation voltage, channel shortening and saturation velocity. The threshold voltage shift and subthreshold slope variation is determined through the minimum value of the potential in the channel. Only eight model parameters are used. The model is physically-based, considers the total charge in the Si layer and the operating conditions in both depletion and accumulation. Model is validated by 2D simulations in ATLAS for channel lengths from 25 nm to 500 nm and for doping concentrations of 5 × 1018 and 1 × 1019 cm-3, as well as for Si layer thickness of 10 and 15 nm, in order to guarantee normally-off operation of the transistors. The model provides an accurate continuous description of the transistor behavior in all operating regions.
- Compact core model for Symmetric Double-Gate Junctionless Transistors(2014) Cerdeira A.; Avila F.; Iniguez B.; De Souza M.; Pavanello M.A.; Estrada M.A new charge-based compact analytical model for Symmetric Double-Gate Junctionless Transistors is presented. The model is physically-based and considers both the depletion and accumulation operating conditions including the series resistance effects. Most model parameters are related to physical magnitudes and the extraction procedure for each of them is well established. The model provides an accurate continuous description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of being symmetrical with respect to drain voltage equal to zero. It is validated with simulations for doping concentrations of 5 × 10 18 and 1 × 1019 cm-3, as well as for layer thickness of 10 and 15 nm, allowing normally-off operation. © 2014 Elsevier B.V.
- Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors(2013) Cerdeira A.; Estrada M.; Iniguez B.; Trevisoli R.D.; Doria R.T.; De Souza M.; Pavanello M.A.A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors (SDGJLTM) is proposed and validated with simulations for doping concentrations of 5 × 1018 and 1 × 10 19 cm-3, as well as for layer thicknesses of 10, 15 and 20 nm. The model is physically-based, considering both the depletion and accumulation operating conditions. Most model parameters are related to physical magnitudes, and the extraction procedure for each of them is well established. The model provides an accurate description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of the requirement of being symmetrical with respect to Vd = 0 V. © 2013 Elsevier Ltd. All rights reserved.
- Trap density characterization through low-frequency noise in junctionless transistors(2013) Doria R.T.; Trevisoli R.D.; De Souza M.; Pavanello M.A.This work evaluates, for the first time, the trap density of Junctionless Nanowire Transistors (JNTs) of two technologies produced with different gate dielectrics through the low-frequency noise (LFN) characterization. Along the work, the LFN resultant from both devices was compared in linear and saturation regimes for different gate biases, showing that these devices can exhibit either 1/f or Lorentzian as the dominant noise source depending on the technology and gate bias. Such analysis showed that devices with SiO2 gate dielectric have presented only one corner frequency over the whole frequency range whereas two corner frequencies with different time constants could be observed in devices with HfSiON gate dielectric. The trap density of both devices showed to be similar to the values reported for inversion mode devices in different recent papers, in the order of 1016 cm-3 eV-1 and 1019 cm-3 eV-1, for SiO2 and HfSiON gate dielectrics, respectively.© 2013 Elsevier B.V.All rights reserved.