Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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2 resultados
Resultados da Pesquisa
- Analysis of the output conductance degradation with the substrate bias in SOI UTB and UTBB transistors(2018-08-31) FERNO COSTA, J.; TREVISOLI, R.; Rodrigo Doria© 2018 IEEE.The goal of this work is to present the behavior of the output conductance in Ultra-Thin Body (UTB) and Ultra-Thin Body and Buried Oxide (UTBB) SOI {MOSFETs with the application of a selected set of back gate biases (VSUB) through AC simulations, in devices with and without considering the effect of the ground plane. It has been shown that the output conductance degradation due to self-heating and substrate effects increases as the substrate bias is reduced. The output conductance degradation by self-heating presents a reduction of about 52% and by substrate effects of 57% by simply increasing the back bias from-2V up to 2 V.
- Influence of the intrinsic length on the behavior of PIN diodes fabricated on SOI substrates working as solar cells(2018-10-26) SILVA, F.; Rodrigo Doria; Michelly De Souza© 2018 IEEE.This work evaluates the influence of the intrinsic region length on the behavior of PIN diodes fabricated in the substrate of SOI wafers, operating as solar cells. The analysis has been performed in terms of efficiency and fill factor, fundamental parameters for the solar cell characterization. The studied cell has shown efficiency of about 7% to 8% and fill factor with average about 80%. Originally, ungated PIN devices have been considered in TCAD simulations. In the sequence, a gate has been placed over the intrinsic region of simulated devices and different biases (0V and 5V) were applied to compare the results with the ungated ones. Lastly, different operation temperatures have been applied into simulations, aiming to achieve results closer to real operation conditions.