Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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11 resultados
Resultados da Pesquisa
- Impact of using Octogonal Layout Style in Planar Power MOSFETs(2022-08-22) DA SILVA, G. A.; Salvador Gimenez© 2022 IEEE.Previous studies have already shown that the use of alternative gate shapes for planar and tridimensional MOSFETs are capable of boosting their analog and digital electrical performances and their ionizing radiations robustness. In this scenario, this work has the objective to study the impact of the use of octagonal layout style (OCTO), as the basic cell, to the implementing of the Planar Power MOSFET (PPM). The main results of this paper show that the PPM layouted with OCTO layout styles, as the basic cells, are able to improve the drain saturation current (IDS-sat) about 668%%, in relation to that implemented with conventional rectangular layout style, considering that they present the same gate area and bias conditions. Therefore, this type of layout approach can be considered an alternative layout to improve the electrical performance of PPMs.
- Comparative study between conventional and wave planar power mosfets(2021-08-27) SILVA, G. A. D.; Salvador Gimenez©2021 IEEE.One of most challenges of nanoelectronics area is to further increase the integration capacity and electrical performance of Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs). Several approaches have been done to reach this challenges, as for instance, the use of different fabrication processes, new transistors structures (bi and tridimensional), new materials etc. An alternative strategy, in which it is capable of reducing the total die area, mainly of the analog Complementary MOS (CMOS) integrated circuits (ICs), without affecting their electrical performance, is the use non-standard gate geometries (Diamond, Octo, Ellipsoidal, Fish, Wave etc.) for MOSFETs, instead of the rectangular one commonly used today. Previous studies have shown that by using Wave MOSFETs as a basic cell of the Planar Power MOSFETs (PPM) was able to reduce their total die areas. Therefore, the motivation of this paper is to verify by experimental data, the electrical behavior of PPM implemented with Wave layout style in relation to the one of PPM layouted with the conventional rectangular MOSFETs. The CMOS ICs technology used to manufacture these devices was of 350nm-ON Semiconductor. The main finding of this work is that the Wave MOSFET used as a base cell of a PPM (Wave PPM) present a similar electrical characteristics, but it is responsible to reduce in 9.7% its die area in comparison to the one found in PPM layouted with conventional MOSFETs and therefore, the Wave layout style is an alternative layout to reduce the total die area of PPM. c2021 IEEE.
- Innovative layout styles to boost the MOSFET electrical performance(2014-01-05) Salvador GimenezThis paper describes how to potentiate the electrical performance of MOSFETs using non-conventional layout styles (rectangular gate geometry), without causing any extra burden to the current ICs manufacturing CMOS process. This layout approach is based on "drain-channel region-source interfaces engineering", which is capable to add new effects to the MOSFET structure that contributes to improve the analog and digital electrical parameters of MOSFETs. Besides that, some of these new structures can enhance the transistor robustness in harsh environment (high temperature and radiation). Furthermore, as a first insight into exploration of this layout approach was applied in Multi-Gate MOSFETs (FinFET) by three-dimensional simulations and the results are very promising. © 2014 The Electrochemical Society.
- Boosting the performance of the planar power MOSFET By using Diamond layout style(2014-09-05) DA SILVA, G. A.; Salvador Gimenez© 2014 IEEE.This manuscript introduces and experimentally investigates, for the first time, the Planar Power MOSFETs implemented with Diamond (hexagonal gate geometry) Metal-Oxide-Semiconductor Field Effect Transistor with different a angles, as a basic cell, in comparison to the homologous Multifinger PPM, regarding the same gate die area and bias conditions. Using the DPPM as output current driver (switch) in digital integrated circuits applications, we can remarkably boost the PPM electrical performance in relation to the MPPM, considering the same gate area (AG) and bias conditions (BC).
- Boosting the radiation hardness and higher reestablishing pre-rad conditions by using OCTO layout style for MOSFETs(2014-09-05) DE SOUZA FINO, L. N.; Marcilei Aparecida Guazzelli; RENAUX, C.; FLANDRE, D.; Salvador GimenezThis manuscript has the objective to perform an experimental comparative analysis of the total ionizing dose influence in the Silicon-On-Insulator Metal-Oxide-Semiconductor Field Effect Transistor implemented with the octagonal gate shape (OCTO) and the standard one (rectangular gate shape) counterpart, after a X-ray radiation exposure. The back-gate bias technique is applied in these devices to reestablish the threshold voltage and subthreshold slope that were degraded by the ionizing radiation effects. Since the octagonal layout style maintains a better electrical performance after radiation, a smaller back-gate bias to recover the pre-rad operation is required in comparison to the conventional counterpart. This is mainly because the parasitic transistors in the bird's beak region are practically deactivated by the particular octagonal gate geometry.
- Using the octagonal layout style to implement the pass MOSFET to improve the electrical performance of the CL-LDO voltage regulator(2018-05-17) MARTUCCI, R. F.; Salvador Gimenez© The Electrochemical Society.This paper presents a study by SPICE simulations and experimental data of a capacitor-less low-dropout (CL-LDO) voltage regulator (VR) by using a novel backend technique to improve its electrical performance. This study regards the use of an octagonal layout style in the pass device MOSFET of a CL-LDO VR to mainly boost its open-loop voltage gain and reduce output impedance. The results show that this innovative layout approach used in the CL-LDO voltage regulator can increase its power supply rejection ratio (PSRR) in approximately 2 dB (60 Hz), without degrading its quiescent current (Iq) (improvement of 2% better), and without wasting additional die area, in comparison to the one that its pass MOSFETs was implemented by using standard rectangular layout style. The 130 nm Bipolar Complementary Metal-Oxide-Semiconductor (BiCMOS) manufacturing process from GlobalFoundries was used to implement both CL-LDO VRs, via MOSIS Educational Program. The die areas of each CL-LDO VRs are the same and equal to 0.00994mm2.
- Boosting the performance of MOSFET operating under a huge range of high temperature by using the octagonal layout style(2019-08-30) GALEMBECK, E. H. S.; SWART, J.; SILVA, G. A.; Salvador Gimenez© 2019 IEEE.This paper performs an experimental comparative study of a huge variation of temperature influence (from 300K to 573K) in planar Metal-Oxide-Semiconductor (MOS) Field-Effect-Transistors (MOSFETs), which are implemented with the octagonal (Octo MOSFETs, OM) and rectangular (Rectangular MOSFETs, RM) layout styles, regarding the same bias conditions. The devices were manufactured regarding a Complementary MOS (CMOS) Integrated Circuits (ICs) manufacturing process of 180 nm. The main results have shown that the OM is capable of keeping active the Longitudinal Corner Effect (LCE) and PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), which are intrinsic present in its structure, resulting a higher electrical performing in the relation to their RM counterparts, such as the OM saturation drain current (IDS_SAT) and transconductance (gm) are approximately three and two times, respectively, better as compared to those found in its RM counterpart. Therefore, the octagonal layout style for MOSFETs can be considered an alternative layout strategy to boost the electrical performance of the MOSFETs, without causing any additional burden to the CMOS ICs manufacturing process.
- Boosting the ionizing radiation tolerance in the mosfets matching by using diamond layout style(2019-08-30) PERUZZI, V. V.; CRUZ, W. S. D.; SILVA, G. A. D.; TEIXEIRA, R. C.; SEIXAS JUNIOR, L. E.; Salvador Gimenez© 2019 IEEE.There are a lot of initiatives to improve the devices matching (dog bone layout, common centroid layout, dummy devices, etc.). Another layout technique, not yet used by integrated circuits (ICs) companies, is the utilization of non-conventional layout styles (hexagonal, octagonal, ellipsoidal, etc.) for MOSFETs, thanks to the Longitudinal Corner Effect (LCE), Parallel Connection of MOSFETs with different channel Lengths Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in Bird's Beaks Regions (DEMPAMBBRE). In this context, this paper describes an experimental comparative study of the devices matching of Metal-Oxide-Semiconductor Field Effect Transistors (130 nm Silicon-Germanium Bulk), n-type (nMOSFETs) implemented with Diamond (hexagonal) and standard rectangular layout styles, regarding a sample of 189 transistors which were exposure to different X-rays ionizing radiations. Considering some relevant electrical parameters considered in this work, the results indicate that the Diamond layout style with α angle equal to 90° is capable of boosting by at least 40% the device matching in relation to one observed with standard (rectangular) MOSFET counterparts in irradiation environment, considering they present the same gate areas, channel widths and bias conditions. Therefore, the Diamond layout style can be considered another hardness-by-design (HBD) layout strategy to boost the electrical performance and ionizing radiation tolerance of MOSFETs.
- Electrical behavior of effects LCE and PAMDLE of the ellipsoidal MOSFETs in a huge range of high temperatures(2020-05-14) GALEMBECK, E. H. S.; Salvador Gimenez© 2020 ECS - The Electrochemical Society.This paper presents the electrical behavior at high temperature-range of the effects presents in the non-standard gate layout style for MOSFETs, in which they are capable to boost the electrical performance in relation to the one standard rectangular MOSFET (RM) counterpart. These effects are named Longitudinal Corner Effect (LCE) and Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE). In this study, we study the ellipsoidal layout style for MOSFET, taking into account the Bulk technology of CMOS CIs of 180nm from TSMC. This work is based on three-dimensional numerical simulations and we conclude that the LCE and PAMDLE effects are always actives in all temperatures studied (300K-573K) and, consequently, they are capable of boosting the EM electrical performance remarkably in comparison to the RM counterpart (83% for saturation drain current and 86% for the maximum transconductance), regarding that present the same gate areas and bias conditions for a temperature of 573K.
- Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs(2021-01-05) BANIN JUNIO, J. R. BANIN JUNIO, J. R.; MORETO R. A. L.; DA SILVA, G. A.; THOMAZ, C. E.; GIMENEZ, S. Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs. Analog Integrated Circuits and Signal Processing, v. 106, n. 1, p. 293-306, Jan. 2021.; MORETO R. A. L.; DA SILVA, G. A.; THOMAZ, C. E.; Salvador Gimenez© 2020, Springer Science+Business Media, LLC, part of Springer Nature.This paper describes a pioneering methodology to design, optimize, and reduce the total gate area of robust Operational Transconductance Amplifiers (OTAs). The Single-Ended Single-Stage (SESS) OTA has been chosen to validate the proposed technique by using the 180 nm planar Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technology. The Electronic Design Automationtool, named iMTGSPICE, was used to design and optimize the SESS OTA. There are several heuristics optimization techniques of Artificial Intelligence to optimize analog and radio-frequency CMOS ICs, but we have selected to use the Genetic Algorithm because it presents the best optimization performance among the other algorithms previously studied. This paper also describes a procedure of converting the Conventional planar MOSFETs (rectangular gate shape) into the Diamond MOSFETs (hexagonal gate shape) with the same electrical performance. Furthermore, it is proposed a procedure to simulate the Diamond MOSFETs (DMs) in the Simulation Program with Integrated Circuit Emphasis (SPICE) because there is still no SPICE model to perform the DM. Additionally, this work proposes a methodology to layout OTAs with Diamond MOSFETs, regarding different values of aspect ratios. The main result of this work reveals a total gate area reduction of approximately 30% of a robust OTA implemented with Diamond MOSFETs, with an alpha angle (α) equal to 45°, with respect to the one observed in the robust OTA implemented with standard MOSFETs, maintaining practically the same electrical performance and robustness.