Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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3 resultados
Resultados da Pesquisa
- Surface-potential-based drain current analytical model for triple-gate junctionless nanowire transistors(2012-01-05) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; DAS, S.; FERAIN, I.; Marcelo Antonio PavanelloThis paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its derivatives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short-channel devices down to 30 nm at different temperatures have been also used to validate the model. © 2012 IEEE.
- Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors(2012-09-02) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloJunctionless nanowire transistors have a constant doping profile from source to drain, providing a great scalability without the need of rigorously controlled doping gradients and activation techniques. Therefore, these devices are considered as promising for decananometer era. This work proposes an analytical model for the drain current in junctionless nanowire transistor (JNT) accounting for short channel effects and temperature dependence. Tridimensional numerical simulations of p-type devices have been performed to validate the model. Experimental data of n-type devices have also been used. © The Electrochemical Society.
- Drain current model for junctionless nanowire transistors(2012-03-17) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloJunctionless Nanowire Transistors (JNT) are considered as promising devices for sub-20 nm era due to the great scalability they provide. This work proposes a physically based analytical model for the drain current in JNTs. The proposed model is continuous from the subthreshold region to the saturation. The model is validated with 3D TCAD simulation and experimental results. © 2012 IEEE.