Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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7 resultados
Resultados da Pesquisa
- Impact of the twin-gate structure on the linear kink effect in PD SOI nMOSFETS(2006-08-05) AGOPIAN, P. G. D.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.In this work, the influence of the twin-gate structure on the gate-induced floating body effects in thin gate oxide partially depleted (PD) silicon-on-insulator (SOI) nMOSFETs is investigated through two-dimensional numerical simulations, which are validated by experimental results. The asymmetric behavior of the body potential with the interchange of the master and slave transistor of the twin-gate structure will be shown, as well as the relation between the total resistance and the effective mobility degradation factor. It will be demonstrated that a similar reduction of the linear kink effect is obtained in a twin-gate structure and in a conventional SOI transistor with an external resistance in series. © 2006 Elsevier Ltd. All rights reserved.
- The temperature mobility degradation influence on the zero temperature coefficient of partially and fully depleted SOI MOSFETs(2006) CAMILO, L. M.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.The zero temperature coefficient (ZTC) is investigated experimentally in partially (PD) and fully depleted (FD) SOI MOSFET fabricated in a 0.13 μm SOI CMOS technology. A simple model to study the behavior of the gate voltage at ZTC (VZTC) is proposed in the linear and the saturation region. The influence of the temperature mobility degradation on VZTC is analyzed for PD and FD devices. Experimental results show that the temperature mobility degradation is larger in FD than in PD devices, which is responsible for the VZTC decrement observed in FD instead of the increment observed in PD devices when the temperature increases. The analysis takes into account temperature dependence model parameters such as threshold voltage and mobility. The analytical predictions are in very close agreement with experimental results in spite of the simplification used for the VZTC model as a function of temperature in the linear and the saturation region. © 2006 Elsevier Ltd. All rights reserved.
- Study of the linear kink effect in PD SOI nMOSFETs(2007-01-05) AGOPIAN, P. G. D.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.We present in this work a study of the linear kink effect (LKE) occurrence in partially depleted (PD) SOI nMOSFETs with thin gate oxide. The experimental LKE dependence on the channel length, channel width and drain voltage are reported as well as the impact of various parameters on the second peak has been studied by two-dimensional numerical simulations, namely, the gate current level, the carrier lifetime, the increase of the body potential, the threshold voltage variation and AC analysis. Three-dimensional simulations were also performed in order to evaluate the LKE dependence on the channel width. © 2006 Elsevier Ltd. All rights reserved.
- Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation(2008) Doria R.T.; Cerdeira A.; Raskin J.-P.; Flandre D.; Pavanello M.A.In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-around (GAA) devices operating in saturation region for analog applications. The study has been performed through device characterization and two-dimensional process and device simulations. The overall study has been done on the total and third order HDs. When applied in the saturation regime as an amplifier, the GC outperforms conventional GAA transistors presenting simultaneously higher transconductance, lower drain output conductance and more than 15 dB improved linearity. The influence of channel length reduction on the HD is also analyzed. Although slight linearity degradation is observed in both the conventional and the GC devices when reducing the channel length, the HD presented by the GC transistor is significantly lower than the one showed by conventional device for any studied channel length. This allows AC input signal amplitude up to 20 times higher than the conventional GAA for a same specified distortion level. © 2008 Elsevier Ltd. All rights reserved.
- Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS(2006) Gimenez S.P.; Pavanello M.A.; Martino J.A.; Flandre D.This paper studies the performance of operational transconductance amplifiers (OTAs) fabricated with Graded-Channel (GC) SOI nMOSFETs and designed to provide high open-loop voltage gain or high gain-bandwidth characteristics. Different design targets were taken in account such as similar power dissipation, transconductance over drain current ratio and die area. Comparisons with OTAs made with conventional SOI nMOSFETs, are performed showing that the GC OTAs presents larger open-loop voltage gain without degrading the phase margin, unit gain frequency and slew rate simultaneously with a significant required die area reduction depending on LLD/L ratio used. Circuit simulations and experimental results are used to qualify the analysis. © 2005 Elsevier Ltd. All rights reserved.
- Evaluation of graded-channel SOI MOSFET operation at high temperatures(2006) Galeti M.; Pavanello M.A.; Martino J.A.This paper presents a comparative analysis between graded-channel (GC) and conventional fully depleted SOI MOSFETs devices operating at high temperatures (up to 300 °C). The electrical characteristics such as threshold voltage and subthreshold slope were obtained experimentally and by two-dimensional numerical simulations. The results indicated that GC transistors present nearly the same behavior as the conventional SOI MOSFET devices with similar channel length. Experimental analysis of the gm/IDS ratio and Early voltage demonstrated that in GC devices the low-frequency open-loop gain is significantly improved in comparison to conventional SOI devices at room and at high-temperature due to the Early voltage increase. The multiplication factor and parasitic bipolar transistor gain obtained by two-dimensional numerical simulations allowed the analysis of the breakdown voltage, which was demonstrated to be improved in the GC as compared to conventional SOI transistors in thin silicon layer devices in the whole temperature range under analysis. © 2005 Elsevier Ltd. All rights reserved.
- Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications(2006) Pavanello M.A.; Der Agopian P.G.; Martino J.A.; Flandre D.We present in this work an analysis of the low temperature operation of Graded-Channel fully depleted Silicon-On-Insulator (SOI) nMOSFETs for analog applications, in the range of 100-300 K. This analysis is supported by a comparison between the results obtained by two-dimensional numerical simulations and measurements in the whole temperature range under study. The Graded-Channel transistor presents higher Early voltage if compared to the conventional fully depleted SOI nMOSFET, without degrading the transconductance over drain current, at all studied temperatures, leading to a gain larger than 20 dB compared to the conventional SOI. The resulting higher gain lies in the improvement of the electric field distribution and impact ionization rate by the graded-channel structure. © 2005 Elsevier Ltd. All reserved.