Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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7 resultados
Resultados da Pesquisa
- Influence of the N-type FinFET width on the zero temperature coefficient(2007-09-07) BELLODI, M.; MARTINO, J. A.; CAMILO, L. M.; SIMOEN, E.; CLAEYS, C.This paper presents the influence of the Fin width dimension on the Zero Temperature Coefficient (ZTC) behavior for devices operating at high temperatures (from room temperature up to 573K). Besides this, a simple analytical model is presented in order to describe the ZTC behavior as the temperature increases. Three-dimensional simulations are carried out and compared with experimental results to support the interpretation presented along this work. © The Electrochemical Society.
- Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs(2008-09-04) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.This work studies the influence of the fin width on the intrinsic voltage gain of standard and strained Si (sSOI) n-type triple-gate FinFETs with high-k dielectrics and metal gate. It is demonstrated that independent of the fin width the application of strain improves the device transconductance. On the other hand, the device output conductance shows a high dependence on the fin width in strained FinFETs with respect to standard ones. The output conductance degrades if narrow fins are used and improves for wide fins. Narrow strained FinFETs show a degradation of the Early voltage compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. © The Electrochemical Society.
- Fin width influence on the harmonic distortion of standard and strained FinFETs operating in saturation(2009-09-03) Rodrigo Doria; CERDEIRA. A.; MARTINO J. A; SIMOEN, E.; CLAEYS, C.; Marcelo Antonio PavanelloThis work compares the harmonic distortion of standard and biaxially strained FinFETs aiming at analog applications such as amplifiers. The harmonic distortion has been extracted for devices operating as single transistor amplifiers. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated for devices with several fin widths. For a fairer analysis, the influence of the open-loop voltage gain (Av) in devices with different dimensions has also been considered generating the figures of merit THD/Av and HD3/Av. According to the analysis, narrower devices have overcome the wider ones and conventional FinFETs have shown to be more attractive than the strained ones for analog purposes. Narrower standard FinFETs exhibited up to 20 dB THD/Av better in relation to the strained ones. © The Electrochemical Society.
- Low temperature and silicon thickness influences on the threshold voltage of double-gate MOSFETs considering a charge based extraction procedure(2009-09-03) Rodrigo Doria; Marcelo Antonio PavanelloThis work studies the influence of the temperature and the fin width (silicon thickness) on the threshold voltage of lightly doped double-gate MOSFETs. The evaluation was performed using tridimensional simulations, device measurements and model. The threshold voltage was defined considering the classical double derivative method and a charge based one, and the results were compared to an analytical model. The charge based definition has shown a better concordance with the analytical model for the influence of both temperature and fin width. The surface potentials extracted at the threshold condition have also exhibited that the charge-based criterion for threshold voltage definition results in closer values to those expected analytically. The variation of the threshold voltage with the temperature is overestimated if it is extracted using the double derivative method in comparison to the charge-based one. Experimental results confirmed the predictions obtained through simulations and model. © The Electrochemical Society.
- Influence of fin width and channel length on the performance of buffers implemented with standard and strained triple-gate nFinFETs(2009-09-03) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion. © The Electrochemical Society.
- Harmonic distortion analysis of SOI triple gate FinFETs applied to 2-MOS balanced structures(2009-05-29) Rodrigo Doria; MARTINO, J. A.; CERDEIRA, A.; Marcelo Antonio PavanelloThis work presents an evaluation of the non-linearities exhibited in 2-MOS resistive structures composed by triple gate FinFETs with several fin widths down to 30 nm. The harmonic distortion has been analysed in terms of its third order component (HD3) as a function of the gate voltage, the input amplitude voltage and the fin width. The linearity has also been analysed with respect to the on-resistance, which constitutes a key parameter in such circuits. Along the harmonic distortion evaluation, the non-linearity causes are pointed out. At lower gate voltages, wider devices present smaller HD3 with respect to the narrower ones, while the contrary occurs at higher gate voltages. ©The Electrochemical Society.
- Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape(2009) Buhler R.T.; Giacomini R.; Pavanello M.A.; Martino J.A.The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (AV), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies. © 2009 IOP Publishing Ltd.