Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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7 resultados
Resultados da Pesquisa
- Analysis of Fin Width Influence on the Carrier's Mobility of Nanowire MOSFETs(2021-08-31) CCOTO, C. U. C.; BERGAMASHI, F. E.; Marcelo Antonio Pavanello©2021 IEEE.In this work, the study of the effective electron mobility (peff) of n-channel MOS transistor nanowires is presented. By extracting the mobility of the top and sidewall using the surface current separation technique together with the split-CV method. Analyzing the comparison of simulated TCAD results and experimental transistors fabricated with various fin widths (12nm-82nm) and how the effect of varying the fin width and applied substrate voltages interfere with carrier mobility values.
- NBTI Dependence on Temperature in Junctionless Nanowire Transistors(2021-07-27) GRAZIANO, N.; TREVISOLI, R.; Rodrigo, Doria©2021 IEEE.This paper discusses the nature of degradation by NBTI effect in pMOS junctionless devices when varying the temperature. The results were obtained through simulations validated to experimental data. Devices with different dimensions and doping, have been subjected to a temperature range that varies between 270 and 380 K. The simulations were performed for different values of VGT and as a result it is possible to observe that when increasing temperature up to 340 K, the threshold voltage variation due to NBTI is also increased. However, for larger temperatures the NBTI effect seems to stabilize or even reduce.
- Junctionless Nanowire Transistors Based Common-Source Current Mirror(2021-08-27) SHIBUTANI, A. B.; SOUZA, M. D.; TREVISOLI, R.; Rodrigo Doria©2021 IEEE.In this article, a current mirror built with junctionless nanowire transistors (JNTs) is investigated for the first time. The study explores the influence of transistors' width on the mirroring precision for input and output devices with different dimensions. The work has been performed through numerical simulations validated with experimental data and showed that the variation of devices' width impacts the output characteristics differently from usually observed in current mirrors formed by inversion mode devices.
- Comparative study between conventional and wave planar power mosfets(2021-08-27) SILVA, G. A. D.; Salvador Gimenez©2021 IEEE.One of most challenges of nanoelectronics area is to further increase the integration capacity and electrical performance of Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs). Several approaches have been done to reach this challenges, as for instance, the use of different fabrication processes, new transistors structures (bi and tridimensional), new materials etc. An alternative strategy, in which it is capable of reducing the total die area, mainly of the analog Complementary MOS (CMOS) integrated circuits (ICs), without affecting their electrical performance, is the use non-standard gate geometries (Diamond, Octo, Ellipsoidal, Fish, Wave etc.) for MOSFETs, instead of the rectangular one commonly used today. Previous studies have shown that by using Wave MOSFETs as a basic cell of the Planar Power MOSFETs (PPM) was able to reduce their total die areas. Therefore, the motivation of this paper is to verify by experimental data, the electrical behavior of PPM implemented with Wave layout style in relation to the one of PPM layouted with the conventional rectangular MOSFETs. The CMOS ICs technology used to manufacture these devices was of 350nm-ON Semiconductor. The main finding of this work is that the Wave MOSFET used as a base cell of a PPM (Wave PPM) present a similar electrical characteristics, but it is responsible to reduce in 9.7% its die area in comparison to the one found in PPM layouted with conventional MOSFETs and therefore, the Wave layout style is an alternative layout to reduce the total die area of PPM. c2021 IEEE.
- The Second Generation of the Layout Styles for MOSFETs to Further Boosting the Electrical Performance of Analog MOSFETs and CMOS ICs(2021-08-27) GALEMBECK, E.H. S.; SILVA, G. A. D.; Salvador Gimenez©2021 IEEE.This article describes, for the first time, the study of electrical behavior of the first element belonging to the family of Second Generation of layout styles for Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), entitled Half-Diamond. It was conceived in order to further boosting the electrical performance of the analog MOSFETs in relation to the one found in Diamond MOSFETs (hexagonal gate shape). This innovative layout style has by objective further enhance the Longitudinal Corner Effect (LCE) and mainly the Parallel Connections of MOSFETs with Different Channel Lengths Effect (PAMDLE) by the means of further reducing of the effective channel lengths of Diamond MOSFETs in relation to those measured in the conventional (rectangular gate geometry) ones (RMs). The main results found by the three-dimensional numerical simulations indicates that the Half-Diamond MOSFET (HDM) is able to provide a saturation drain current 13% higher than the one observed in the RM counterpart. Furthermore, the electrical behaviors of LCE, PAMDLE and DEPAMBRE in HDM are analyzed in detail by observing the electrical behavior of the electrostatic potentials, longitudinal electric fields and drain current densities. c2021 IEEE.
- Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs(2021-08-27) RODRIGUES, J. C.; MARINELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloThis paper aims at analyzing the electrical characteristics of 2-level Stacked Nanowire MOSFETs at low temperatures. Fundamental device parameters such as threshold voltage, subthreshold slope and transconductance are evaluated in the temperature range of 160K to 400K. The influence of fin width variation is also studied. An analytical model of multiple-gate nanowire MOSFETs is employed to explain the experimentally observed data. It is demonstrated that the threshold voltage increases linearly with the temperature reduction. Stacked nanowires with wider fin width presents larger threshold variation with temperature. c2021 IEEE.
- Analysis of Capacitances in Asymmetric SelfCascode SOI nMOSFETs(2021-08-27) ALVES, C.R.; D' OLIVEIRA, L. M.; Michelly De Souza©2021 IEEE.This work presents a study of the capacitance of asymmetric self-cascode silicon-on-insulator (ASC SOI) MOSFETs with similar gate areas and different gate lengths. Experimental results of total gate capacitance of different ASC are presented and complemented with the results of twodimensional simulations. The transcapacitances are explored through two-dimensional simulations. Results show that different channel lengths of the composite transistors have more influence in the depletion region of the capacitance curves for low VDS. The gate-source and gate-drain capacitances show opposite trends with the change in the lengths of source and drain transistors, despite of the VDS applied.