Analysis of Capacitances in Asymmetric SelfCascode SOI nMOSFETs
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Tipo de produção
Artigo de evento
Data de publicação
2021-08-27
Texto completo (DOI)
Periódico
SBMicro 2021 - 35th Symposium on Microelectronics Technology and Devices
Editor
Texto completo na Scopus
Citações na Scopus
1
Autores
ALVES, C.R.
D' OLIVEIRA, L. M.
Michelly De Souza
Orientadores
Resumo
©2021 IEEE.This work presents a study of the capacitance of asymmetric self-cascode silicon-on-insulator (ASC SOI) MOSFETs with similar gate areas and different gate lengths. Experimental results of total gate capacitance of different ASC are presented and complemented with the results of twodimensional simulations. The transcapacitances are explored through two-dimensional simulations. Results show that different channel lengths of the composite transistors have more influence in the depletion region of the capacitance curves for low VDS. The gate-source and gate-drain capacitances show opposite trends with the change in the lengths of source and drain transistors, despite of the VDS applied.
Citação
ALVES, C.R.; D' OLIVEIRA, L. M.; DE SOUZA, M. Analysis of Capacitances in Asymmetric SelfCascode SOI nMOSFETs. SBMicro 2021 - 35th Symposium on Microelectronics Technology and Devices. August, 2021.
Palavras-chave
Keywords
Analog performance; Asymmetric; Capacitance; Mosfet; Self-cascode; Silicon-on-insulator
Assuntos Scopus
Analog performance; Asymmetric; Gate-length; MOS-FET; MOSFETs; nMOSFETs; Self-cascode; Silicon on insulator; Silicon-on-insulator MOSFETs; Two-dimensional simulations